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For my school side project i'm building a digital clock from 40xx series chips. I'm at 11 IC's now, taking up two regular sized breadboards.

While I could simply solder this all onto solderable breadboad, I do also have some PCB perfboard with pre-tinned thru holes. I can't help but wonder if I could somehow condense the layout to make the board smaller. While the breadboard size would work, it leaves my clock a little larger than desired.

Leaves me wondering... How did people even go about routing boards with multiple, maybe dozens of CMOS chips?

For instance:

enter image description here

What baffles me the most is those chips stacked vertically above one another. My project uses 6 CD4026 IC's to divide time. All 6 are connected to one another for carry outs. I can't imagine any other way to arrange them other than one after another, like this:

enter image description here

And here are my boards.. Possible layout?

enter image description here

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    \$\begingroup\$ Multiple layers \$\endgroup\$ – Tyler Jan 9 at 18:32
  • \$\begingroup\$ I mean, yeah Tyler is right. Those PCBs have multiple layers whereas the breadboard only has, well... one so to speak. \$\endgroup\$ – KingDuken Jan 9 at 18:41
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    \$\begingroup\$ For hand assembly, you could place the components closer using wirewrap sockets, and then use wire wrapping tool with 30 AWG wire to make all your connections. Don't forget 0.1uF caps from Power to Gnd at each chip - could even put them on the bottom of each board. See here, with wire wrap tool and wire on page 2 peconnectors.com/wire-wrap-sockets-and-headers Get a few colors of wire - Red for power, Black for Gnd, two others for signals. \$\endgroup\$ – CrossRoads Jan 9 at 18:43
  • \$\begingroup\$ One of my most complex designs had ~88 SMD chips on a 8" x 8" board, with address and data busses and clock and control signals running around. PCB routing guys had some nice tools to route it all on 16 layer boards, with dedicated power and Gnd layers so all the connections could be made without having to snake around power Gnd traces. Two of those boards were mounted back to back on a thick copper heatsink, with 5 row connectors to mount to the backplane, and flex cable over the top of the board to let the two sides talk to each other. \$\endgroup\$ – CrossRoads Jan 9 at 18:48
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    \$\begingroup\$ Note that what you're calling "layout" is usually called "placement" or "parts placement" -- "layout" refers to both placement and routing (where the copper goes). Your general placement is OK for a start, but you want (A) allow more room around your chips, and (B) always always always put a decoupling capacitor from VCC to ground on each chip -- a 100nF ceramic should be just fine. They don't cost much, and they save you from having all sorts of inexpiable behaviors. \$\endgroup\$ – TimWescott Jan 9 at 20:31
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The classic layout technique with double-sided boards that mostly contain DIP packages is to run traces (primarily) vertically on one side and primarily horizontally on the other. Power is routed first to keep the traces low inductance, and bypass capacitors are placed at every chip, usually. Typically the power pins are at the corners.

That technique is pretty useless in the current year because SMT packages often have leads on each side, and the level of integration is much higher.

If you're using perf board you should take care of the power and bypassing first and then run the signal lines. Your proposed layout looks fine to me. I've done many prototype perf board setups using polyester solder-through magnet wire (in the distant past, now it's easier and better to lay out a PCB and have it manufactured). Here's the back of an LED display board for an instrument prototype:

enter image description here

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    \$\begingroup\$ Customer: I accidentally cut the gold wire... :) \$\endgroup\$ – rdtsc Jan 9 at 19:14
  • \$\begingroup\$ "because SMT packages often have leads on each side" What? Do you mean parts that have pins on all four sides? I do quite a bit of board design with PLCC and other "xxxLCC" parts, with two layers, just fine. You have to violate the strict "vertical/horizontal" rule a bit around the pins, but for the most part it works. \$\endgroup\$ – TimWescott Jan 9 at 20:27
  • \$\begingroup\$ @TimWescott Yes, I mean on all 4 sides. I'm drawing a comparison with the strict grid layout of chips common in the 80s. Of course you have to have localized traces running on one side or the other primarily on a 2-layer board or you end up with a ton of vias but seems more like the directions change depending on where you are on the board and which side the parts are on, particularly for tight boards. \$\endgroup\$ – Spehro Pefhany Jan 9 at 20:35
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Wirewrapping - this box was all wirewrapped for connections. LEDs were soldered in place, didn't make sense for sockets for those. And then I wirewrapped right to the LED legs, which are square pins. 8 conductor cables (Dupont-style crimp housing headers with female-female wires) were made up to connect from the back of the card in the middle (what looks like empty sockets are really socket strips) to the back of the LED boards (more socket strips) to drive the 7-segment displays from a MAX7219. I used this for 8 years at my fencing club before we closed up.

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  • \$\begingroup\$ May I ask what that board is used for? I love those 7 segments you made.Very cool. Edit: Ok so you used it for fencing club. Is that a scoreboard? \$\endgroup\$ – StrugglingStudent117 Jan 9 at 19:05
  • \$\begingroup\$ It's a fencing scoring machine. Both fencers connect to it, it detects when a touch is made. A warble tone is played (you can't see the small speaker at the bottom), one or both large blocks of LEDs light up. Has a running 3 minute time that the referee starts, and stops automatically upon a touch (bottom 4 digits). Referee controls score on the 2 upper digits on the left and right. Small digits in the middle keep track of the fencing period (1 to 3, or up to 9 for a team event), and show the weapon type in use (S, F, E). Groups of 2 yellow and red for warnings or penalty for each side. \$\endgroup\$ – CrossRoads Jan 9 at 19:12
  • \$\begingroup\$ Did you use transistors to pwr those LED’s? \$\endgroup\$ – StrugglingStudent117 Jan 9 at 19:17
  • \$\begingroup\$ No, MAX7219 drove them all. Each segment is 3 LEDs in parallel. I probably have a transistor to drive the 2 blocks of touch lights, I do see current limit resistors there. Been 10 years, I'd have to look up what I used. \$\endgroup\$ – CrossRoads Jan 9 at 19:28
  • \$\begingroup\$ The LEDs in the segments were all from the same batch, they seemed to match well current-draw wise, and the MAX7219 outputs were set to a relatively current as it turns out the LEDs were really bright - like blinding bright! \$\endgroup\$ – CrossRoads Jan 9 at 19:51
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Tyler mentioned this - don't know why he didn't frame it as an answer. But it's basically multiple layers on the board, at least for commercial applications (not hobbyist). Pretty much everything we do now is 14 layers minimum, up to 40 layers or more. Yeah, they're thick! At least 2 return planes, 6 or 8 routing layers, and no circuitry on the top & bottom layers.

Sometimes the layer count is driven by having to break out traces from high density pin count packages.

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