# Can you split track width among layers to equal one big trace?

Assume you want a trace to be able to carry 20 amps of current on 1oz copper with a temperature rise of 20. Using an online calculator this yields 12.60mm trace width.

My question is, can you split that width among bottom and top layers (6.30mm each) and stitch together those layers using vias? If so, is there any special considerations with this method?

• If they are directly opposite each other on the PCB, the temperature rise is likely to be closer to 40C as both heaters are heating the same small area of PCB. Jan 10, 2020 at 21:46
• good point @BrianDrummond
– Alex
Jan 10, 2020 at 21:56
• Electric Stove/Oven makers often wave or solder dip with a certain fill pattern to enhance thick solder coating on copper fill areas to 20A relays just to save a few pennies from using a busbar. Jan 10, 2020 at 22:26
• @TonyStewartSunnyskyguyEE75 i read that wasn't really all that effective, and remember seeing dave over at eevblog crapping on that technique. these are low-run boards that i'm designing to switch landscape light transformers with. 2oz copper would be my go-to for this, but drastically increases the prices of the boards. I figured if I split the difference between top and bottom layers i'd have a manageable trace/polygon size, and then I would probably introduce exposed copper areas in the planes so i can solder larger gauge wire over (poor mans busbar).
– Alex
Jan 10, 2020 at 22:30
• Soldering solid bus wire is fine for low volume or (braid for low inductance applications) I might estimate 2 coplanar heater tracks to only reduce temp rise by 25% rather than 50% as the ambient on 1 side is shared Jan 10, 2020 at 22:35

1 - Yes. With attention to detail by both you and the board house, you can move a hundred amps with +/-10% sharing.

2a - The internal traces will run warmer than the external ones. Some online calculators address this.

2b - Pay attention to the vias; they have a large impact on how evenly the current is spread among the layers. Depending on the board stackup, you might have 2 oz copper traces but only 1 oz copper in the vias. If you want to get picky about it, a via is a very short trace whose width is equal to the hole circumference. Use the hole diameter minus one plated copper thickness as the diameter. This is equivalent to the average of the inside and outside circumferences of the copper tube.

Also, while it is good to spread out some vias along the trace run, the clusters of vias around the ends (or any high-current branches) have the biggest impact on current sharing.

• hole diameter equivalent to drill diameter? the software i use says "diameter" and "drill diameter". my understanding is that the inside e.g. drill diameter is what gets plated so that is the diameter I should use for the via current calcs right?
– Alex
Jan 10, 2020 at 22:00
• Yes. The difference between the drill diameter and the finished plated diameter is two times the copper thickness. Jan 11, 2020 at 2:33

At the very least, you need to do some derating as the two traces are not going to share current exactly 50-50. When we parallel connector pins, we add 25% to the calculated number of pins and round up. I think we do the same thing with wires. So as a SWAG I would add 25% to your calculated trace widths.

I don't think we've ever done that. We would either increase the trace width appropriately, or go with heavier copper, which would be 2 oz Cu in your case.

The current carrying capacity of a trace is determined by the cross sectional area and the length. Another factor to consider is temperature rise.

If you have one trace that is 1000mil x 50mil, they will have the same resistance as two traces with dimensions of 1000mil x 25mil.

So yes, you can spit a 12.6mm trace into two 6.3mm traces. One other thing to consider is that if vias are used for stiching, they also need to be able to handle the current, and vias also add small amounts of resistance. So use a current carrying calculator for vias and make sure you have a sufficent number of vias and size of vias.