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I have an application in mind in which I need to communicate via SPI with an FPGA. Both the FPGA and microcontroller are in our control, and so I have the flexibility to define the protocol as I see fit. However, I was wondering if there are any good example uses out there that work well.

Here is what I was thinking. (byte oriented)

Master: <REG><WR+LEN><MSTR_DATA><CHK>
Slave : < 0 ><  0   ><SLAV_DATA><CHK>

REG : register within FPGA to read or write
WR  : read / write bit
LEN : 7 bit payload length (not including REG,WR+LEN or CHK)
MSTR: master data if write mode.
SLAV: slave data if read mode.
MCHK: 8 bit checksum of MSTR_DATA (by master), (CRC8, XOR, mod 256 etc)
SCHK: 8 bit checksum of SLAV_DATA (by slave ), (CRC8, XOR, mod 256 etc)

Is this workable? Are there any better examples out there?

EDIT1: Some clarification on requirements:

  • The microcontroller is to read and write small blocks of data to/from the FPGA.
  • The FPGA will support read/write operations to registers.
  • The registers can be many bytes deep (like a fifo) or autoincrementing (next read or write byte comes from the next register).
  • I would like the operation including the checksum / ack to occur in a single transmission.
  • I would like this have a low overhead, some operations will be fetching or posting 5-10 bytes. The largest could be 127 or 64.
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2 Answers 2

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I would have a look at Modbus and HDLC Asynchronous framing for examples of how to transfer packets over a serial bus. I would also have a look at this question Simple serial point-to-point communication protocol over on Stack Overflow.

Edit:

Since you are in need of low overhead I would just do what you are doing. Use Chip select to gate the packet and include length and checksum. I would probably stay away from CRC8 as your data is byte based not bit based. I checked several SPI memory devices and none of the ones I looked at included a checksum.

One example of a check sum is the UDP checksum. For your example that would translate to the ones complement of the sum mod 256.

For ack or status back from slave you can take advantage of the fact that SPI is full duplex and instead of just sending nothing back the slave can just send a status byte and in that byte you can use one bit to flag checksum errors. The status can also include a busy bit so you can use this to poll the slave to see when it is done and ready for another command.

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  • \$\begingroup\$ I am familiar with those protocols. SPI doesn't share the same characteristics as RS485/RS232 etc.. SPI is syncronous and is restricted to being master / slave.... the slave has no control over how many bytes the master sends or attempts to receive. Additionally, this protocol needs to be lightweight, chip to chip. Modbus and HDLC are device to device. \$\endgroup\$
    – JeffV
    Commented Oct 2, 2010 at 19:35
  • \$\begingroup\$ Thanks, I am currently using the same technique without the len and chgecksum. It is basicaly very similar to most of the other uses I've seen of SPI. \$\endgroup\$
    – JeffV
    Commented Oct 3, 2010 at 0:02
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I believe SD card SPI mode has a checksum.

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    \$\begingroup\$ SD cards have checksums for some parts of the protocol, but they're usually ignored in SPI mode. Only the first command (which puts the card in SPI mode) must have a valid checksum. \$\endgroup\$ Commented Oct 2, 2010 at 14:13
  • \$\begingroup\$ @reemrevnivek, you're right. I'm looking for a protocol that allows me to perform large and small transactions with the FPGA and be confident they are error free. (which makes me think I would need a way for the master to know that the slave failed its check. The overhead is going to add up if I need a final slave acknowledge... Hmmm....) \$\endgroup\$
    – JeffV
    Commented Oct 2, 2010 at 14:31
  • \$\begingroup\$ I built a similar custom I2C interface with a checksum years ago. Now starting a fresh SPI project I’m also wondering what examples I might be able to draw from. WRT to the master knowing about failure you could stuff useful bits in the first 2 slave bytes indicating if a past transaction failed CRC \$\endgroup\$
    – asdf30
    Commented Jun 16, 2021 at 3:21

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