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Well, for educational purposes I've decided to make an FPGA-based board with PCIe, HDMI and other high-speed stuff.

I've usually used relatively slow (35-45 ns) SRAM and having traces routed in 'hit or miss' style works just fine. Now I've decided to use a few IS61WV204816BLL-10TLI 10 ns SRAM chips.

Also, I want to use AS6C6416-55BIN SRAM as they are relatively compatible in pin-out. I have never routed fast parallel busses myself. In my head, I had a rule that everything above 50 MHz must be routed in some smart way.

I've had a read of various articles and got out few things:

  1. Length and impedance matching are two very different things
  2. Length matching has meaning when you have fast rise/fall times
  3. Documentation must somewhere state need of length/impedance matching
  4. Each bus (data, address, control) should preferably be routed on its own layer. As I understand it, this is for better impedance.

As far as I can see, the documentation of the chips I plan to use doesn't state the need for these techniques. But, out of interest, I did this:

img1 (power planes are omitted)

All traces are matched within 1 mm. Furthermore, I found out that using 90 deg or 45 deg bends may cause reflections and it is better to use arcs. Does this look okay?

img2

So I have a bunch of questions:

  1. Have I made things worse? Should I just run straight lines?
  2. When exactly (overall frequency or edge time) do I need to start length matching?
  3. Is impedance matching necessary in my case?
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  • \$\begingroup\$ Why does you artwork show the traces going to the pads for the BGAs rather than to the dog bone vias, on the 2nd picture? \$\endgroup\$ – SteveSh Jan 11 at 0:13
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    \$\begingroup\$ @SteveSh, that's the top layer, looks like orange, green, and purple layers do go to dog bones. \$\endgroup\$ – Austin Jan 11 at 7:03
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In my opinion, your design looks good with the exception of impedance matching. I'm also assuming you do have ground reference planes stacked-up between signal layers.

Assuming you want to achieve full read/write speeds, the datasheet for this SRAM IC states:

Test conditions assume signal transition times of 1.5 ns or less

(Page 8: http://www.issi.com/WW/pdf/61-64WV204816BLL.pdf)

Taking that 1.5ns value and using a rule of thumb for lumped vs distributed circuit, you find that if all your traces were below 1.5inch (38mm), no length matching is required: http://fullychargd.blogspot.com/2017/02/transmission-line-rules-of-thumb.html

I do not know the trace length (you haven't mentioned, they look pretty short) however I do see that your board has the layers and space which makes me believe you did great by using this opportunity to length match.

Cornering reflection issues won't be a problem for <10G signals. Take a look to this article (which is based on Dr. Howard Johnson. results): https://resources.altium.com/pcb-design-blog/pcb-routing-angle-myths-45-degree-angle-versus-90-degree-angle

It is however preferred to remove the sharp corners to avoid creating acid traps, which you have done properly in your design.

For better signal integrity and system reliability, impedance matching is important, both at design and manufacturing level. However, for a personal project, I would skip the manufacturing part (expensive) and only focus on sizing the trace width following your own stackup calculation (Saturn PCB or equivalent software will do). Impedance matching within +/-10% should give you good results and is commonly used in the industry.

As I mentioned above, it does seem like all your SRAM signals on all layers have the same width which probably means you haven't sized them yet. I would highly recommend putting focus on this aspect before sending it out for fabrication.

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I don't think you have to length-match the traces.

In write mode, the critical timing parameter is from when the last (slowest) address or data line is valid, relative to the WE.

In read mode (OE controlled), the critical timing parameter of from when the last (slowest) address line is valid, relative to the OE.

By putting the meander line lengths in, you're just making all of the address or data bits have the same prop time as the slowest one.

Edit 1:

I would use controlled impedance for all the traces. This is something most PWB vendor can do as a matter of course, meaning that it doesn't take much effort on their part and doesn't cost you anything.

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  • \$\begingroup\$ I always thought controlled impedance traces cost quite a bit extra? Or does controlled impedance mean something different than what I think it means? \$\endgroup\$ – DKNguyen Jan 11 at 8:24
  • \$\begingroup\$ Thanks for the answer! But why you have to length-match DDR2+ memory then? No one of my two usual PCB fabs provide impedance matching. But CAD I'am using has built-in feature of controlling track width for all nets in same netclass. So widths will be different on each layer. Idk how you can controll impedance other way than controlling track width. \$\endgroup\$ – batyastudios Jan 11 at 9:01
  • \$\begingroup\$ Besides track width, trace impedance is affected by the proximity of the trace to a reference plane, be it Vcc or GND, Along with this, it's affected by whether the trace is a microstrip or stripline.implementation. We usually give our PCB vendors instructions on a target impedance, say 50 ohms +/- 20%, and give them the latitude to adjust trace widths and layer spacing (with constraints) to meet the target impedance goal. \$\endgroup\$ – SteveSh Jan 11 at 17:58
  • \$\begingroup\$ @ DKNguyen - My comment is based on doing 12 layer and up PCBs, where reference planes are readily available and we have 6 or more routing layers to use. Obviously, controlled impedance is going to be much more difficult, if impossible, to achieve on a simpler double sided (2 layer) PCB \$\endgroup\$ – SteveSh Jan 11 at 18:03
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I've had a read of various articles and got out few things:

  1. Length and impedance matching are two very different things
  2. Length matching has meaning when you have fast rise/fall times
  3. Documentation must somewhere state need of length/impedance matching
  4. Each bus (data, address, control) should preferably be routed on its own layer. As I understand it, this is for better impedance.
  1. Correct
  2. Length matching has meaning when you have fast switching cycles / clock speeds. Fast rise/fall times alone doen't need length matching, they need impedance matching.
  3. This is sometimes mentioned in the datasheet, but not always. There might be an application note or something about these requirements though.
  4. Not necessarily. It is recommended though to route the whole bus on a single layer, to achieve better matching (both length and impedance), but you can route several buses on the same layer.

So I have a bunch of questions:

  1. Have I made things worse? Should I just run straight lines?
  2. When exactly (overall frequency or edge time) do I need to start length matching?
  3. Is impedance matching necessary in my case?
  1. Signal integrity point of view, you have not done it worse, it works the same as the straight lines. Your design just takes some more space compared to the straight lines.
  2. When the skew in the trace length starts to break setup and hold times. The signal travels roughly 15 cm/ns. If the requirement is roughly 1ns, you can tolerate 15 cm difference in the traces (well, it is not actually quite this simple calculation, but it should give you a ball park figure).
  3. Most likely it will work just fine without matching. With short traces the ringing caused by the mismatch is a minor problem. In the datasheet it doesn't mention that there would be any termination or impedance matching in the component. Thus if you want to avoid ringing (and the noise it might cause) you need to use series termination resistors that match the trace impedance. Then you can match the resistors to what ever value the trace impedance happens to be. This can be done by measuring the ringing and adjusting the resistor value until the ringing is minimized.
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