Well, for educational purposes I've decided to make an FPGA-based board with PCIe, HDMI and other high-speed stuff.
I've usually used relatively slow (35-45 ns) SRAM and having traces routed in 'hit or miss' style works just fine. Now I've decided to use a few IS61WV204816BLL-10TLI 10 ns SRAM chips.
Also, I want to use AS6C6416-55BIN SRAM as they are relatively compatible in pin-out. I have never routed fast parallel busses myself. In my head, I had a rule that everything above 50 MHz must be routed in some smart way.
I've had a read of various articles and got out few things:
- Length and impedance matching are two very different things
- Length matching has meaning when you have fast rise/fall times
- Documentation must somewhere state need of length/impedance matching
- Each bus (data, address, control) should preferably be routed on its own layer. As I understand it, this is for better impedance.
As far as I can see, the documentation of the chips I plan to use doesn't state the need for these techniques. But, out of interest, I did this:
All traces are matched within 1 mm. Furthermore, I found out that using 90 deg or 45 deg bends may cause reflections and it is better to use arcs. Does this look okay?
So I have a bunch of questions:
- Have I made things worse? Should I just run straight lines?
- When exactly (overall frequency or edge time) do I need to start length matching?
- Is impedance matching necessary in my case?