DDR4 board bringup issue

I am struggling with a DDR4 related board bringup issue. Can anyone out there recognise what the problem is by studying the attached memory dumps?

The memory dump is from Preboot loader PB31 area of RAM that consists mainly of strings. It has a 50-byte data area of 0's followed by a string of 50 'a' characters followed by a string of 50 'b' characters.

• The one to the left has been made by target code itself running from SRAM (Preboot loader PB2 code).
• The one to the right has been extracted from a JTAG connected debugger.

They memory dumps show a very distinct error pattern:

• The one to the left clearly shows that a 17-bits area that repeats itself every 32 bytes is in error.
• The one to the right clearly shows that a 17-bits area that repeats itself every 16 bytes is in error.

The difference between the two could be influenced by memory access type. The data read is consistent across reboots. The error is the same on the two tested boards so far.

• The DRAM consists of 2 x Micron MT40A512M16LY-062E_IT (DDR4-3200).
• The data bus width is 32 bits (2 x 16 bits). No ECC.
• The DDR bus rate is 650 Mhz (1300 GT/s).
• The SoC is a NXP LS1027A

Here is a text copy of the data in image to the left that contains the zeros, a's, and b's at the end:

0F E0 EF 01 03 00 00 00 1D 00 10 00 59 00 14 00
0F 00 04 00 00 1D 2A 0D 37 37 2F 35 6C 73 5F 70
6F E1 FF 5F 73 69 70 5F 68 61 6E 64 6C 65 72 00
0A 25 73 3A 20 75 6E 68 61 6E 64 6C 65 64 20 53
4F E3 EF 28 30 78 25 78 29 0A 00 14 53 45 43 20
69 73 20 64 69 73 61 62 6C 65 64 2E 0A 00 14 53
4F E3 FF 20 53 49 50 5F 53 56 43 5F 32 5F 41 41
52 43 48 33 32 20 46 61 69 6C 65 64 2E 0A 00 00
EF E4 FF 87 FC ED 09 42 A4 23 8D 23 75 9D 3B 9F
6C 73 5F 73 69 70 5F 73 76 63 00 00 00 00 00 00
0F E0 EF 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0F E0 EF 00 00 00 00 00 00 00 00 00 00 00 14 42
4C 33 31 3A 20 25 73 0A 00 14 2A 42 4C 33 2E 20
6F E1 EF 61 61 61 61 61 61 61 61 61 61 61 61 61
61 61 61 61 61 61 61 61 61 61 61 61 61 61 61 61
6F E1 EF 61 61 61 61 61 61 61 61 61 61 61 61 61
61 61 00 14 2A 42 4C 33 2E 20 62 62 62 62 62 62
6F E2 EF 62 62 62 62 62 62 62 62 62 62 62 62 62
62 62 62 62 62 62 62 62 62 62 62 62 62 62 62 62
6F E2 EF 62 62 62 62 62 62 62 62 62 00 14 2A 42
4C 33 2E 20 25 73 00 0A 45 4C 31 20 73 75 70 70


Here is a text copy of the data in image to the right that contains the zeros, a's, and b's at the end:

0F E0 EF 01 03 00 00 00 1D 00 10 00 59 00 14 00
0F E0 EF 00 00 1D 2A 0D 37 37 2F 35 6C 73 5F 70
6F E1 FF 5F 73 69 70 5F 68 61 6E 64 6C 65 72 00
0F E5 FF 3A 20 75 6E 68 61 6E 64 6C 65 64 20 53
4F E3 EF 28 30 78 25 78 29 0A 00 14 53 45 43 20
6F F3 EF 64 69 73 61 62 6C 65 64 2E 0A 00 14 53
4F E3 FF 20 53 49 50 5F 53 56 43 5F 32 5F 41 41
5F E3 EF 33 32 20 46 61 69 6C 65 64 2E 0A 00 00
EF E4 FF 87 FC ED 09 42 A4 23 8D 23 75 9D 3B 9F
6F F3 FF 73 69 70 5F 73 76 63 00 00 00 00 00 00
0F E0 EF 00 00 00 00 00 00 00 00 00 00 00 00 00
0F E0 EF 00 00 00 00 00 00 00 00 00 00 00 00 00
0F E0 EF 00 00 00 00 00 00 00 00 00 00 00 14 42
4F F3 FF 3A 20 25 73 0A 00 14 2A 42 4C 33 2E 20
6F E1 EF 61 61 61 61 61 61 61 61 61 61 61 61 61
6F E1 EF 61 61 61 61 61 61 61 61 61 61 61 61 61
6F E1 EF 61 61 61 61 61 61 61 61 61 61 61 61 61
6F E1 EF 14 2A 42 4C 33 2E 20 62 62 62 62 62 62
6F E2 EF 62 62 62 62 62 62 62 62 62 62 62 62 62
6F E2 EF 62 62 62 62 62 62 62 62 62 62 62 62 62
6F E2 EF 62 62 62 62 62 62 62 62 62 00 14 2A 42
4F F3 EF 20 25 73 00 0A 45 4C 31 20 73 75 70 70


The Preboot loader code is based on the reference board design (LS1028ARDB). The DDR controller configuration is as follows:

struct dimm_params ddr_raw_timing = {
.n_ranks = 1,
.rank_density = PLAT_DEF_DRAM0_SIZE, // 0x80000000 (2GB)
.capacity = PLAT_DEF_DRAM0_SIZE, // 0x80000000 (2GB)
.primary_sdram_width = PLAT_DEF_DRAM_WIDTH, // 32
.ec_sdram_width = 0,
.rdimm = 0,
.mirrored_dimm = 0,
.bank_group_bits = 1,
.edc_config = 0,
.tckmin_x_ps = 625,
.tckmax_ps = 1900,
.caslat_x = 0x017FFC00,
.taa_ps = 13750,
.trcd_ps = 13750,
.trp_ps = 13750,
.tras_ps = 32000,
.trc_ps = 45750,
.twr_ps = 15000,
.trfc1_ps = 350000,
.trfc2_ps = 260000,
.trfc4_ps = 160000,
.tfaw_ps = 21000,
.trrds_ps = 2500,
.trrdl_ps = 4900,
.tccdl_ps = 5000,
.refresh_rate_ps = 7800000,
.dq_mapping[0] = 0x6,
.dq_mapping[1] = 0x27,
.dq_mapping[2] = 0x9,
.dq_mapping[3] = 0x2B,
.dq_mapping[4] = 0x9,
.dq_mapping[5] = 0x23,
.dq_mapping[6] = 0x3,
.dq_mapping[7] = 0x2B,
.dq_mapping[8] = 0x0,
.dq_mapping[9] = 0x0,
.dq_mapping[10] = 0x0,
.dq_mapping[11] = 0x0,
.dq_mapping[12] = 0x0,
.dq_mapping[13] = 0x0,
.dq_mapping[14] = 0x0,
.dq_mapping[15] = 0x0,
.dq_mapping[16] = 0x0,
.dq_mapping[17] = 0x0,
.dq_mapping_ors = 0,
.rc = 0x1f,
};


The dq_mapping is according to the board layout.

Very grateful for any pointers! Thank you

• Code? Schematic? Layout? – filo Jan 11 at 14:19
• Thanks filo. I have edited question to include relevant code. I will check on monday what I may include of schematic and/or layout. – Rolf Peder Klemetsen Jan 11 at 14:53
• dram is debugged with a scope for DDR4 this is a very very expensive scope, about the price of a nice house and the probes about the price of a used car. Cant really do much without that. and someone who knows the protocol and someone who knows the controller to know how to move components of the transaction around or adjust amplitudes. with that equipment it can take days to months to get working. seems you have made it a long way so is this protocol/settings or is it noise or power, termination, pcb, etc? – old_timer Jan 11 at 16:34
• Yes old_timer, I know. This has taken much time already. I hope someone out there has seen the same pattern memory corruption and can share their findings. – Rolf Peder Klemetsen Jan 11 at 18:12