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I was going through the uCurrent project and noticed something that seemed unusual to me. In the image, the trace connecting R1 to the input jack is (a) of differing trace widths, and (b) has no solder mask for a small portion.

Does anyone know if there's a reason for a small portion of the trace to be different from the rest? I can't think of an electrical reason, except maybe controlling the trace impedance with a different trace width but that doesn't explain why there's no solder mask. Is the exposed trace meant to help during testing?

There's no solder mask

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    \$\begingroup\$ Please add in a link to the project rather than assume we are all familiar with it. \$\endgroup\$ – Transistor Jan 12 at 19:43
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    \$\begingroup\$ Poor man's fuse? If you can't get a good answer here, it would be a good idea to ask on Dave Jones' EEVblog forums. \$\endgroup\$ – evildemonic Jan 12 at 20:39
  • \$\begingroup\$ @Transistor, apologies for that. Thank you @ Andrew Morton for the edit. Fuse seems like an interesting possibility. I think I will go to the EEVBlog and post the same thing. Thank you \$\endgroup\$ – acexa616 Jan 12 at 21:48
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    \$\begingroup\$ I wonder: The older version which has a description states it has NO FUSES. Moreover, would a fuse not add to the burden voltage they desperately try to reduce? \$\endgroup\$ – Huisman Jan 12 at 21:49
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    \$\begingroup\$ To help other readers here, this is the link to the same question now asked on the EEVblog forums, if anyone wants to follow the topic there. \$\endgroup\$ – SamGibson Jan 12 at 22:19
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I wanted to answer my own question in case someone is interested. This bottleneck was a fusible track. The EEVBlog forum had a discussion on this.

The idea of the trace is that it would fuse and protect some of the components on the PCB in case of a very large current input. The temperature rise of the fuse seems to be dictate by the trace width, material used for plating and the substrate surrounding the same. However, this is not a replacement for a standalone fuse.

Additional reading on fusible tracks: http://www.cetti.ro/cadence/articles/New_Methods_of_Testing_PCB_Traces_Capacity_and_Fusing.pdf

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