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In pipeline ADCs, there is an amplifier after each stage that amplifiers the remainder of the previous stage by 2^(number of previous stage bits - 1). For example, if the flash ADC in the first stage is 3-bit, the remainder is amplified by a factor of 4. This leads to an overlap bit between the stages. My question is, why do we need this overlap bit, and why don't we remove it to get the maximum number of output bits from the ADC?

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    \$\begingroup\$ I haven't ever designed one or examined them as closely as you appear to have. But what you write makes me imagine that the reasoning my follow along similar lines as for a "partial products multiplier" tree. It will be educational for me to see good answers on this. I may be way, way off-base. \$\endgroup\$
    – jonk
    Commented Jan 12, 2020 at 22:41

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this happens because this bit that is overlaped, we don't trust its value. Can exist some offset error. There may be some error in this last bit and you don't want to pass this error to the next phases. I recommend you read the following link, maybe it helps and explains it better than me: Digital Error Correction and this: ADC Offset Error

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I never designed a pipeline ADC and never studied it carefully, but I designed a SAR ADC with redundancy before.

In a perfect world, where the comparators have no offset, no noise, where the reference voltage has zero source impedance, etc, you don't need an extra bit per stage. However, in the real world due to the noise of the comparators, offset or other non idealities (that I am not completely aware in the pipeline ADCs), you can have an error in the result of one of the stages. If you have only N bits for N effective bits, you can't recover from an error like this and get the right conversion result. Why? Because you only have one output code for a certain range of Vin values. Therefore, in ADCs people use frequently redundancy. This means that the ADC determines more bits than the effective number of bits that you are looking for. At the end of the conversion, you convert these bits into the right number of bits. Since the raw result has more bits, it has more possible combinations. If done right, you now have several possible codes for the same Vin range. Therefore, if you make a mistake in one bit, you can still recover from that mistake, since there are more output codes available that correspond to the right Vin.

As I said, I never learned about redundancy in pipeline ADCs. I could give you some references for papers about it in SAR ADCs. Tell me if you are interested.

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