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What is the point of an upper byte and lower byte enable on an SRAM if the data bus is already 16-bits?

Is it related to multiplexing? I had always assumed that SRAMs were either designed with either multiplexed or dedicated data and address buses. Maybe I am wrong and they all have dedicated buses and how you wire them up determines whether or not they are multiplexed. Seems like you wouldn't save many pins or traces that way though. It would only save them MCU pins, but would not affect the SRAM pins or the number of traces running between the two ICs.

I am looking an an MRAM Datasheet, though this seems broadly applicable to all SRAMs: https://www.everspin.com/family/mr5a16a?npath=258

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Upper and lower byte enables are needed when a processor with a 16-bit bus wants to do an açcess to modify just one half of the data RAM location.

For byte write operations this greatly increases performance over having to do a 16-bit read-modify-write operation.

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  • \$\begingroup\$ Is this standard operating procedure do I need to figure out if the MCU supports this? \$\endgroup\$ – DKNguyen Jan 14 at 1:41
  • \$\begingroup\$ @DKNguyen which MCU? \$\endgroup\$ – Bruce Abbott Jan 14 at 2:01
  • \$\begingroup\$ @BruceAbbott An STM32H743. NBL[0:3] are the byte lane pins. \$\endgroup\$ – DKNguyen Jan 14 at 2:09
  • \$\begingroup\$ STM32 External Memory Control page 20. \$\endgroup\$ – Bruce Abbott Jan 14 at 2:49
  • \$\begingroup\$ @BruceAbbott Ah, so its called Byte Enable \$\endgroup\$ – DKNguyen Jan 14 at 2:54
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Usually when I've seen that, they share an 8bit data bus. I agree that for a 16bit data bus, it would not be used, both UB and LB should be low. This chip puts the upper byte on different pins from the lower byte and alternately sets the other 8 bits to Hi-Z, so they can still be tied together (0,8) (1,9) etc.

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