What is the point of an upper byte and lower byte enable on an SRAM if the data bus is already 16-bits?
Is it related to multiplexing? I had always assumed that SRAMs were either designed with either multiplexed or dedicated data and address buses. Maybe I am wrong and they all have dedicated buses and how you wire them up determines whether or not they are multiplexed. Seems like you wouldn't save many pins or traces that way though. It would only save them MCU pins, but would not affect the SRAM pins or the number of traces running between the two ICs.
I am looking an an MRAM Datasheet, though this seems broadly applicable to all SRAMs: https://www.everspin.com/family/mr5a16a?npath=258