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I'm referring to one answer here

https://i.stack.imgur.com/JyQtz.png

What if (power supply) was 24V, the VCC is 3v3 delayed by 1 second?

If you apply power then your (power loss detect) will be higher than the Vcc rail for 1 second? I don't imagine this to end up well.

In my mind i need an (and gate) that is activated by the CPU. But that will cost one more GPIO, so we can activate it from VCC itself.

However, is that and gate really required or there is better solution?

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  • \$\begingroup\$ If power was 24 volts then Vcc would be about 23 volts and frying your CPU. \$\endgroup\$
    – Andy aka
    Jan 15, 2020 at 10:31
  • \$\begingroup\$ Andy aka, if R1,R2 were right they will form a voltage divider and provide 3v3 to cpu \$\endgroup\$ Jan 15, 2020 at 10:34
  • \$\begingroup\$ Then they won't be useful for power loss detect and, resistor dividers don't make very good and stable voltage sources. \$\endgroup\$
    – Andy aka
    Jan 15, 2020 at 10:35
  • \$\begingroup\$ Andy aka, thats not true, this is very common way to put high voltage signals into a gpio. its not power source to the chip it will just divide the original signal, the gpio it self will have very high impedance so it doesnt matter, originally i would replace R2 with a 3v3 zener.. \$\endgroup\$ Jan 15, 2020 at 10:46
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    \$\begingroup\$ I think the problem was your phrase "provide 3v3 to cpu". I thought you meant provide the cpu with power. And maybe you should relabel your diagram as "supply to CPU voltage regulator" rather than Vcc to CPU. \$\endgroup\$
    – Andy aka
    Jan 15, 2020 at 10:49

1 Answer 1

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Yes your circuit can work but could be improved.

If you apply power then your (power loss detect) will be higher than the Vcc rail for 1 second? I don't imagine this to end up well.

If your potential divider impedances are high enough, the current that could be pushed into an IO pin will be low. The data sheet will hopefully advise you that, in the event of Vcc still rising on the CPU, you should be OK. However, if you use a schottky diode from the R1/R2 node to the CPU's Vcc rail AND put an extra resistor in series with the input pin you should be fine: -

enter image description here

Also, if your input pin can be configured to "use" hysteresis (like a Schmitt trigger) then that would be better because, you will have more defined logic levels and most (if not all) UVLO circuits I have seen have hysteresis to prevent a series of glitchy "detections" as the supply is falling through the area where the input gate is most sensitive to non-digital levels.

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  • \$\begingroup\$ thanks, this was my version, Zener instead of shottky because duplicate part,, snipboard.io/HS71aA.jpg ,, what do you think ? \$\endgroup\$ Jan 15, 2020 at 11:25
  • \$\begingroup\$ probably R12 need to be reduced to 50k or less .. \$\endgroup\$ Jan 15, 2020 at 11:27
  • \$\begingroup\$ D18 might be a bit of a spoiler in that it will be conducting above 3 volts and add more uncertainty. You don't need it. I don't understand your choice R12 and R25 values but, I guess if you do have D18 then that explains it. D17 won't make a very good schottky diode because it's forward volt drop might be 0.8 volts. \$\endgroup\$
    – Andy aka
    Jan 15, 2020 at 11:37
  • \$\begingroup\$ hi, so this is better: snipboard.io/Hg7tKv.jpg ? i know extra parts but they are less BOM list.. \$\endgroup\$ Jan 15, 2020 at 12:00
  • \$\begingroup\$ That won't protect the IO line because if the junction of R12 and R26 rises above 3.3 volts then what stops it rising further? \$\endgroup\$
    – Andy aka
    Jan 15, 2020 at 12:05

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