For a PLL, you can define a design spec for clock phase jitter and lock-in time based on the number of cycles of the input frequency to achieve a certain settling time phase error maximum. One tradeoff is the clock jitter is desired to be the lower of the input f or VCO phase noise but starts the sum of two signal phase noise now made worse wit the 2f signal 1 octave higher which is limited by a -6dB for a 1st order filter. A 2nd order filter attenuates 2f better but degrades lock-in range and lock-in time due to the reduction of stability. This is the phase margin reduction by phase-shift at the Δf error frequency.
The simple concept is the phase detector avearge DC voltage pulls the VCO frequency so we integrate that time in cycles until locked-on or < tbd % Phase error. But this has too much jitter and may have an offset phase error, so we loop filter higher DC gain like a true integrator but still have BW or -3dB breakpoint of the loop filter the VCO worst case initial error Δf=f1-f2 yet attenuate the 2f that causes jitter one octave up. (-6dB/octave)
Linear gain/attenuation, Kp but no filter
The fastest lockin time is one with no filter and minimum initial frequency error but also maximum jitter noise control voltage. It has a rise time to 90% or 99% or 99.9% of the final VCO control voltage that depends on the initial frequency error and the tuning range gain of VCO and linear limits of any stage, such as 180 deg or the integration of the mixer's initial frequency error. So the ideal lock-in time with no jitter filter with that integration time of initial frequency error.
So to achieve less jitter with 0 frequency error but not compromise lockin time too much, we add a LPF or true integrator. Then to improve stability we make a combination 1st order attenuator (no filter) and true integrator filter combination that approaches an ideal compromise. A further enhancement is a lock detector that stabilizes the noise even more with an analog switched filter to reduce the jitter once it is locked-on.
If the break point is too low for the initial frequency error then the PLL will skip cycles and take too long by going thru negative-feedback pull-in, then positive-feedback push away. If the filter is too low f , it will never be able to pull-in to Lock-on.
The example I have in my simulation has an intentionally large VCO error with a control range from 15 to 75 Hz to track 50Hz. I could have easily chosen 45 to 55 Hz but then the VCO error budget must not exceed 4~5Hz over all component and ambient stress variables and mfg tolerances. I could have chosen a VCXO with an initial tolerance of 10 ppm with a TCXO of 1ppm and a tuning range of 15 to 20 ppm or a OCXO of 10 ppb and a digitally tunable range of 15 ppb. Or I could have chosen a Rubidium OCXO with excellent frequency stability but terrible phase noise and then lock a Crystal VC-OCXO which far superior phase noise but worse initial frequency error. There are also digital shift register or delay line phase detectors that can be corrected in 1 clock cycle for phase but still have a frequency error that must be corrected for the sampling interval. By using a counter after the VCO or f-division, this multiplies the VCO frequency. Then dividing outside the loop yields a ratio or a fractional-N synthesizer. This done by Intel, AMD and Broadcom in almost every CPU to save on power and heat rise by using a clock like the 100MHz FSB clock to make a fractional-N synthesis of the 100MHz clock to some GHz value.
In short there are hundreds of ways to implement PLL's with any frequency.
It is possible to design a LPF that with good SNR signal quality is near critically damped and defined the RC=T time constant in terms of N/Δf for the initial Δf error.
The requirement for PLL stability may be expressed as a quadratic function of PID gain constants , Initial frequency error/LPF BW attenuation,DC loop gain and phase margin at unity gain .
Simulation Shows how the Mixer integrator of f = Phase error and True Integrator DC gain of 1e5, result in "~ zero" phase error. Here demonstration with 9k R pulled high to reduce f and increase initial Freq. error, to demo , 2nd order overshoot.
PID overshoot, settling time values and capture range are improved with 10% series R in series with C, but more jitter.