Shared bus in FPGA (arbiter + perypherial bus) [VHDL]

Question

I am trying to implement shared bus in my fpga design. I am thinking about something similar to the microcontroller bus.

I see two possibilies:

Second option is easier to implement but if bus is wide it will be more resources used. Something which is in my opinion optimal for my requirements is proposed in "Option 1". This approach requires three state buffers. Do you think it is achievable on FPGA ? Does anybody have some examples of code for design like this ??

Best regards, Kamil

Answer 1

As FPGAs^* do NOT support on-chip tri-state drivers you can not implement option-1 on them.

You should go for the MUX version.

^*_{At least I don't know any FPGA of reasonable size which still has them.}