I am trying to implement shared bus in my fpga design. I am thinking about something similar to the microcontroller bus.
Second option is easier to implement but if bus is wide it will be more resources used. Something which is in my opinion optimal for my requirements is proposed in "Option 1". This approach requires three state buffers. Do you think it is achievable on FPGA ? Does anybody have some examples of code for design like this ??
Best regards, Kamil