Understanding PLL VCO Integrator Phase-shift

Question

In many PLL phase loop theory discussions, it's often said that the VCO acts as an integrator and therefore has a 90 degree phase shift. I've seen derivations of the VCO transfer function and this image (taken from here) is particularly enlightening:

Here we see the integrating behaviour of the VCO where Vcontrol is integrated to produce a phase that rotates forever around the time axis.

So, $$\theta(s)=K_{vco}\cdot \frac{V_{control(s)}}{s}$$

What I'm having problems with is the "90 degree phase shift" part. I understand that integrators have a 90 degree phase shift and the classic example is the RC low-pass filter. Here the phase shift between input and output voltage can be understood by the voltage/current phase relationship of the capacitor.

But, I'm struggling to understand the 90 degree phase difference of the VCO in a similar intuitive way (especially since the product of the integration is phase). I assume it's between the phase output and some reference. But, I'm struggling to see what that reference is. Is it the control voltage? But, then that's a DC voltage, right? Can anyone help me out?

Answer 1

In the time domain, the VCO output is

w(t)=w,n + Ko*Vc(t) with VCO constant Ko and control voltage Vc(t)

For Vc(t)=0 the nominal frequency is w,n.

With w=d(phi)/dt

we arrive at an integral function for phi(t).

Applying the Laplace transform, we have

PHI(s)=Ko*Vc(s)/s.

That means: The 90 deg phase shift is between the VCO phase and the control voltage Vc(t). Note this control voltage is not a DC voltage but can vary - in particular during the lock-in process. Even under locked conditions Vc(t) is not a fixed DC voltage but swings (a little) around the "locked" point.

Answer 2

When you see the triangular phase error it means the VCO servo loop is going from negative feedback to positive feedback in constant motion until no cycles are slipped. The filter design an VCO drift and initial tolerance error ,play a huge roll (no pun intended) in capturing the incoming frequency and nulling the frequency error.

Since it is a quadrature detector (90 deg offset when locked) the loop error DC voltage will drift to the average value for the VCO that matches the incoming frequency. This VCO could be an RC wide tuning range VCO like my example below or a TCVCXO ovenized ultra stable 1 part per billion frequency error being tuned to a GPS clock.

The factors that control the filter's "VCO error Capture Range" and final phase jitter with sub harmonic sidebands and phase noise are beyond the scope of this question, but the tradeoffs are jitter and lock-in time.

This example is fairly quick but not the fastest PLL design but also high in phase noise. I intentionally Selected R to offset the VCO initial error by >50% upon power Reset but it still tracks 50 Hz in about 80 ms or 4 cycles. To get faster lock-in time and much lower phase noise requires, some other tricks like dual bandwidth analog switches and a lock detector or some other digital method.

Answer 3

Is it the control voltage? But, then that's a DC voltage, right?

If it were a DC (non-changing) voltage it wouldn't be any good for controlling anything.

Where we'd see 90° phase shift is if in your graph instead of varying \$V_{control}(t)\$ with a step function, we varied it with a sinusoid. Then the \$\phi(t)\$ function would also be a sinusoid, and it would lag the \$V_{control}(t)\$ signal by 90°.