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I use this circuit the circuit to obtain pulses as close as possible to the input signal pulses on the 1.5 Ohms resistor. The MOSFET is FPQ50N06 and the transistor is BC239. The circuit gives good results on 25 kHz, 4.8 Vpp and 1.5 V offset. However, I need 200 kHz, 4.8 Vpp and 1.5 V offset. How can I make it work when the signal is 200kHz? (I connect oscilloscope probes shown on the scheme and I exactly need on channel2 (CH2) the pulses shown on the other image which is an oscilloscope screen.the desired pulses with blue signal (yellow is the input))

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  • \$\begingroup\$ Offset?? Please try to be more precise in describing your problem \$\endgroup\$ – Navaro Jan 17 at 23:14
  • \$\begingroup\$ Looks like too weak gate drive. What does the datasheet tell you about switching times? \$\endgroup\$ – winny Jan 18 at 14:15
  • \$\begingroup\$ Mark, Have you tried just swapping out the NFET with an NPN BJT and using a DC blocking capacitor in series with your source resistor? I think it should work fine at 200 kHz. \$\endgroup\$ – jonk Jan 18 at 18:26
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You have a massive power MOSFET with a lot of capacitance. If you reduce the size of the MOSFET you can go faster, or change the type to a different technology than silicon.

A cheap one that should show a lot (like 5 or 10:1) improvement is the FDD1600N10ALZ.

They're cheap enough, but you can run some simulations to see what the predicted performance is. You can also try reducing the 600\$\Omega\$ if that's not enough improvement.

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It seems to me like you could just use an emitter follower circuit. If you do this with the NPN transistor then the output voltage would just be Vout=Vd-0.6

If you need a current then just scale the output resistor accordingly.

If this answer isn't enough then you need to restate the problem in a more complete way.

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There are a few problems with your layout , I can imagine from your resonance.

The 10:1 probe 10pF to 15pF causes Drain resonance with your wire jumper inductance from Vcc low ESR 5V Cap to Drain @ 10nH /cm. Solution add 50 OHm series near drain for a test pin

The inductance in the power to drain increases the resonant gain which can be reduced by using at least hal the length of a few cm in the Source to Rs resistor to ground.

Eliminate 600R gate resistance to drive with 50 Ohm gen. ~ 0 to 10V .

Summary: to decrease Q of resonance; Add series 50R to Drain for probe capacitance and add wire inductance between source and Rs to gnd. Also increase base load to 1k with 1k pullup to gate to Drain for negative feedback.

With these loads it draws 14W peak from the 5V supply and >5W peak in the FET when driven properly as below draws 0.25W Avg or < 2%.

enter image description here

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Basically, in a FET, lower RdsON means a bigger chip which means higher Qg, higher capacitance, ie a slower FET and higher gate drive current if required to switch fast.

RdsOn i sonly relevant if you use the FET as a switch, ie fully turned on. Since your circuit uses the FET in linear mode, RdsON is not a relevant selection criteria for your FET. There will be about 3V across the FET when it is ON. So using a very low RdsON FET results in high capacitance which only makes it slower, but it does not lower dissipation since the FET is never used as a switch.

You need a FET with a lower capacitance, and a driver capable of pushing more current into the gate. I simply added a push-pull driver and the simulator thinks it will work:

enter image description here

Note I picked a random one from the simulator library, so don't use that reference, instead please carefully select the FET, something like:

Vds > 10V

Id > 5A (depends on your current)

RdsOn about 100-200 mOhms at Vgs=4.5V -- This is mostly to make sure it will be well into linear mode at Vds=3V and 0.6A. Check the Id vs Vgs graph in the datasheet (graph below), green operating point is OK, red is not OK as the FET behaves as a resistor so it will need much larger gate voltage swing to control the load, which means it will take more time to charge/discharge the gate.

enter image description here

Qg as low as possible ; be aware that Qg spec depends a lot on the Vds at which is is specified...

SOA should not be violated when the FET is ON in linear mode, so you need a FET that is usable in linear mode, not just switching, so probably not a TrenchFET.

enter image description here

You could try FQP13N06 or FQP10N20 (above graphs are from FQP10N20). Spehro's FDD1600N10 looks even better.

You can also use a BJT, for example D44H11 which should be a good fit. However you will need to adjust your signal generator to add a bit of negative offset voltage, the low level part of the waveform should be about -0.5V to make sure Q2 really brings the power transistor's base down to almost 0V to fully turn it off when it needs to. Or use a more complicated driver circuit.

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Ignoring the ringing (Which might just be poor scope probe technique) you see basically straight line rise and fall, which says to me that the mosfet capacitance is introducing a slew rate limit.

Pick a mosfet with much smaller gate capacitance's or lower the 600R resistor (or both).

Or go with a BJT in place of the mosfet, will need a little base current but should be faster.

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