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Description

I have the following diagram in which a switch connected to a 5V source should control two PNP transistors. I've spent a few hours trying to further understand PNP transistors to better understand what I am doing wrong, but I still can't seem the get anywhere. The logic, as I understand it, should be as follows: SW1 is not conducting = Q1 has emitter connected to GND and is conducting = Q2 cannot connect the emitter to GND and thus is open = Vout is 0V.

Simplified logic:

  1. SW1 not conducting = Q1 conducting = Q2 not conducting= Vout 0V
  2. SW1 conducting = Q1 not conducting = Q2 conducting = Vout 3.7V

schematic

simulate this circuit – Schematic created using CircuitLab

The problem:

The problem I'm having is no matter what the state of SW1 is, Q1 seems to be at 3.7V on the collector pin. Curiously, Vout is also at 3.7V.

Thank you in advance for any help!

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    \$\begingroup\$ Which pin of Q1 is always at 3.7 V? Please use the terms "conducting" and "not conducting" rather than "open" and "closed" - some beginners use "open" to mean conducting, and some mean not conducting. You should have a resistor of 1K or so between SW1 and Q1 base. \$\endgroup\$ – Peter Bennett Jan 18 at 1:28
  • \$\begingroup\$ where is the SW2? \$\endgroup\$ – jsotola Jan 18 at 1:43
  • \$\begingroup\$ @PeterBennett Thank you for the suggestions! I have edited my post to reflect the mistakes/omissions yourself and jsotola pointed out. PeterBennett, any resistor less than R1 being placed between SQ and Q1 would be advised, or is there a specific formula I am needing to use? Without it, is it possible I am frying my transistors? \$\endgroup\$ – PyFire Jan 18 at 1:52
  • \$\begingroup\$ You need a resistor between the switch and Q1 base to limit the base current and prevent damage to the transistor. Q1 collector cannot go below 3.0 V, as there can only be 0.7 volts across Q2's base-emitter junction. \$\endgroup\$ – Peter Bennett Jan 18 at 3:39
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Here's the circuit you have, drawn slightly differently:

schematic

simulate this circuit – Schematic created using CircuitLab

Here, you can see that if the switch isn't closed, then \$R_1\$ pulls \$Q_1\$ into an active-on saturated state, causing \$Q_2\$ to be off. However, this means the collector of \$Q_2\$ is floating (very high impedance.) If you want \$V_\text{OUT}\$ to be a well-defined value, you'll need to pull down its collector with a passive resistance of some kind. This means something like this:

schematic

simulate this circuit

Now, if the switch isn't closed, \$R_3\$ will pull \$V_\text{OUT}\$ down towards ground and this will cause \$V_\text{OUT}\$ to be close to the ground voltage (via \$R_3\, obviously.)

If the switch is now closed, then \$Q_1\$ is off and this allows \$R_2\$ to turn \$Q_2\$ on, and this will pull \$Q_2\$'s collector close to its emitter so that \$V_\text{OUT}\$ is very close to \$Q_2\$'s emitter voltage of \$+3.7\:\text{V}\$.

So AnalogKid's answer is a good one. Just pull down the collector of \$Q_2\$ with a resistor and it will be much better when you measure it with a voltmeter.

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There is nothing explicitly wrong with the schematic, but for more stable operation it is incomplete.

Add a 1 K - 10 K resistor from the Q2 collector to GND. This will assure that Q2 leakage current has somewhere to go when Q2 is off, and you will get a firm 0.0 V reading.

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