module foo (A, B, C, Y); input A, B, C; output Y; reg Y; assign Y = (A && B); endmodule
Produces the error
Register is illegal in left-hand side of continuous assignment when I compile with modelsim, but not with Verilator. I'm guessing this is because they are set to different versions of the Verilog standard. Is that why? Or is this just a tool difference? Modelsim is configured to use "default" Verilog but doesn't say what that is, and verilator advertises supporting many versions but I'm not passing any command line arguments to customize it there either.