"Register is illegal in left-hand side of continuous assignment" in modelsim but not verilator

Question

module foo (A, B, C, Y);                    
   input  A, B, C;          
   output Y; 

   reg    Y;                

   assign Y = (A && B);
endmodule 

Produces the error Register is illegal in left-hand side of continuous assignment when I compile with modelsim, but not with Verilator. I'm guessing this is because they are set to different versions of the Verilog standard. Is that why? Or is this just a tool difference? Modelsim is configured to use "default" Verilog but doesn't say what that is, and verilator advertises supporting many versions but I'm not passing any command line arguments to customize it there either.

Answer 1

According to the Verilator documentation

If no language is specifed, either by this option or +<lang>ext+ options, then the latest SystemVerilog language (IEEE 1800-2017) is used.

In SystemVerilog it is legal to have one (and only one) continuous assignment to a variable.

According to the Questa/Modelsim Documentation

If you use the -sv argument with the vlog command, then Questa SIM assumes that all input files are SystemVerilog, regardless of their respective filename extensions. If you do not use the -sv argument with the vlog command, then Questa SIM assumes that only files with the extension .sv, .svh, or .svp are SystemVerilog.

Answer 2

If what you say is correct then the answer is simple: Verilator is wrong, Modelsim is right.

You can NOT use an assign with a reg as LHS variable type.

Answer 3

Of course you can't do a continuous assignment to a register - that violates the whole concept of what a register is. A register samples the input at the clock edge.