# PFC controller - How does it work?

I would like to better understand how a PFC controller works, especially PFC which work in CCM mode. I found the following documentation from International Rectifier: https://www.infineon.com/dgdl/an-1077.pdf?fileId=5546d462533600a40153559563801007 which deals with the mechanism of a PFC converter. The mechanism is described at page 4: "One Cycle Control for PFC".

Here is what is described:

I know that the result duty cycle should look like to this:

What I understood: The main goal of a PFC is to put the input current in phase with the input voltage. In order to do this, if Vin (rectified) increases, the total variation of Iin (Ioff + Ion) across the inductor during the switching period must be superior to 0 in order to increase. It means that the Ion variation must be superior to Ioff variation. And inversely if Vin (rectified) decrease. Besides, the voltage output must be regulated to an output which is constant! So if Vin increases, we have to reduce the duty cycle in order to transfer less energy to the load and inversely when the input voltage decrease. This is exactly what we see in the above waveforms.

What I did not understand is how the controller works to do what we see on the above waveforms.

Suppose Pout is constant over the time. If Vin decreases, the energy transferred to the load decreases as the variation of the current across the inductor is lower, the the output voltage decreases, so the error amplifier voltage increases, it means that the slope of the integrated error amplifier voltage increase, then if Pout is constant as Vout is lower than previously, Iout which is proportional to Isense increases. So the slope of "-GdcRsIsense" (there is a minus) will increase, and it will tends to decrease the duty cycle where as we want to transfer more energy to the output in order to have a constant output voltage? Where is my error?

Thank you very much!

• Could it be that you're confusing the regulation within one half-cycle with the regulation of average power? Vout is approx. constant over the cycle, while the regulation of the current has to follow the instantaneous shape of the input voltage. For PFCs, the input power has a 100 Hz component but the average input power corresponds to the average output power Jan 20, 2020 at 10:32
• Also, are you looking for an explanation on how PFCs work or this control scheme in particular? Jan 20, 2020 at 13:26
• Hi, you re right ! I didn't have time to look again what I didn't understand. I will take a look later ! I m looking for how PFC controllers work. Thank you for your answer :)
– Jess
Jan 21, 2020 at 7:37

In general

PFC converters in general have to fulfill two criteria. Firstly, the input power equals the output power (neglecting converter losses), meaning that \begin{align} V_{in,rms} \cdot I_{in,rms} = V_{out} \cdot I_{out} \end{align} Secondly, the shape of the input current has to follow the shape of the input voltage to ensure high power factor and with as little harmonic content as possible to fulfill THD criteria. The consequence of these criteria is that the output power will have a fluctuation of double the grid frequency. The effect on the dc side is normally handled by including a large output capacitance.

Control scheme

For explaining the details of a PFC circuit and controller, I like to base it on a boost converter operated in CCM with a simplified control scheme with a cascaded control.

The outer control loop starts by comparing the measuring the output voltage, $$\v_{meas}\$$, to the reference voltage level, $$\v_{ref}\$$. The resulting error, $$\e_{volt}\$$, is fed to a voltage controller (PI$$\_{v}\$$). The controller output can be thought of as the needed average or RMS current needed to feed the output load. In the next step, this value is multiplied with a dimensionless signal that gives a instantaneous current that is the same shape as the grid voltage with zero phase shift, $$\i_{ref}\$$. Again, the reference current is compared to the measured value, $$\i_{meas}\$$, to produce an error signal, $$\e_{current}\$$, which is fed to the current controller (PI$$\_i\$$). The current controller output can be thought of as the instantaneous duty cycle, $$\d\$$, for the boost converter switch, Q. The duty cycle is transformed to a PWM signal by comparing it to a sawtooth signal. The duty cycle over a half period will start high, then decrease, and then go high again towards the end. This is the same as in your figure "c)", where the duty cycle follows the grey area.

This circuit is fairly simple to setup in a simulator, making sure that the current controller has a bandwidth much higher than $$\2 \cdot f_{grid}\$$ and low bandwidth for the voltage controller. The measured output voltage also typically has a filter on it.

Your referenced control system will function in a similar manner, just with a different implementation. Of course, more complex control schemes exist.