# BJT high frequency analysis

I have a little bit of confusion on how the textbook author is determining the high frequency cutoffs for the parasitic capacitance parameters for a common emitter amplifier. This is Boylestad Electronic Devices and Circuit Theory 11th edition. For the analysis, he treats $$\ C_s\$$, $$\ C_c\$$, and $$\C_E\$$ as shorts since, at these higher frequencies, these high pass-filter capacitors will be low impedance. This makes sense to me.

He ends up with two high frequency cutoff frequencies (both a low-pass filter effect) as follows:

$$\ f_{Hi} = \frac{1}{2 \pi R_{THi}C_i}\$$

Where

$$\ R_{THi} = R_{sig}//R_1//R_2//\beta r_e\$$

with

$$\ r_e \approx \frac{26mV}{I_{EQ}} \$$

and

$$\ C_i = C_{Wi} + C_{be} + C_{Mi} = C_{Wi} + C_{be} + (1-A_{VL})C_{bc} \$$

So $$\ C_{Wi} \$$ is input wiring capacitance, $$\C_{be}\$$ is the base to emitter junction capacitance, and $$\ C_{Mi}\$$ is the Miller effect capacitance due to $$\ C_{bc}\$$ feedback from input to output.

$$\ A_{VL} \$$ is the loaded pass-band gain (though not accounting for the AC voltage source series resistance)

The other cutoff frequency is determined by:

$$\ f_{Ho} = \frac{1}{2\pi R_{THo}C_o} \$$

where

$$\ R_{THo} = R_L//R_C \$$

and

$$\ C_i = C_{Wo} + C_{ce} + C_{Mo} = C_{Wo} + C_{ce} + (1-\frac{1}{A_{VL}})C_{bc}\$$

Again the miller effect is seen on the output side.

The author goes through a numerical example, and using these formulas I get the same results.

However, when I simulate this circuit in LTSpice (being sure to convert the NPN model to an "ideal" NPN, and manually insert the shown capacitors), I'm seeing that only one of the break frequencies is close (the break frequency closest to the pass-band, aka the -3dB frequency). However, the other break frequency seems to consistently off by almost exactly +1 decade (higher frequency than calculated).

I'm curious if someone can explain why this is, or indicate the correct way to calculate both cutoff frequencies.

Here is my LTSpice simulation: And here is the plot I'm seeing: So from the math, I get a cutoff at 689kHz and 18MHz, but checking where the asymptotic lines cross, I am seeing more like 700kHz (good) and 120 MHz (bad).

On the other hand, if I compute the values of Ci and Co using the equations, and reform the simulation to use these values directly: I am getting a much closer match to the textbook example (700kHz and 18MHz) : So it's either the textbook isn't calculating the equivalent miller capacitors correctly, or the simulation isn't handling the feedback capacitor (Cbc) quite correctly.

• @SittinHawk Why do you have 406.29 pF on one schematic and 6 pF on the other? Is that because of your calculation that you believe it should be?
– jonk
Jan 19, 2020 at 20:19
• The first schematic has the original configuration of the capacitors. The 2nd schematic has the "equivalent" capacitors using the Ci and Co equations. If the textbook theory holds true, I believe I should get identical results. But I'm not. Jan 19, 2020 at 20:26
• @SittinHawk Have you tried using the .model values for capacitors? They are not static, they change with polarization. Look in the manual (F1) under LTspice > Circuit Elements > Q. ... to see which values for the capacitances you need to use (there are two models). Jul 9 at 14:38
• Just a remark. You measure the voltage of one node. What is the applied formula? Is it v(Vo)/v(V2) as I do ? Or something else? If I remember well, isn't: Avl = V(Vo)/v(Vb)? Jul 11 at 12:40
• Is anyone just checking in the real world :-) ? Jul 13 at 16:57

From what I remember, the Cbe depends on the emitter current.

Higher current causes lower reac (1/gm); at 1mA, its 26 ohms. at 2mA its 13 ohms 2mA is 4 volts / 2Kohm (ignoring the emitter bypass cap).

Thus your circuit has an incremental emitter-base small-signal resistance of about 13 ohms.

If the 2N2222 has 160MHz Ftau, the emitter-base needs 1nanosecond time-constant, or 1,000 picoSeconds TAU.

Given 1,000 pS TAU, and R of 13 ohms, the needed capacitance is 80 pisoFards.

However the large emitter bypass capacitor may influence this.

I decided to simulate this amplifier in LTspice as well.

The circuit: And the frequency response matches the OP's original frequency response. Since in AC analysis LTspice is using linearize BJT's mode. I decided to draw (in LTspice) my own small-signal model and compare the results. And I've got exactly the same result as previously. So the frequency responses are perfectly matched. Very good.

Now let us see what we get if we apply the Miller approximation to the Cbc. And the frequency response is And the close-up As we can see the frequency response above the first pole frequency does not match anymore with the original circuit after we applied the Miller approximation. And this is what OP observed in his simulation. So, we can conclude that the Miller approximations give us the correct placement of a first pole only (dominant pole).

• Aha! This sounds like a winner. And related keywords find: peer.asee.org/… Jul 12 at 15:34
• This is nice. +1. Can you also try with the .model parameters for Cbe & co, instead of external ones? There may be differences. Jul 12 at 17:56
• @aconcernedcitizen Sure I could do that, but then in AC analysis, I would have to change the capacitance value to Cbe = 61.6pF Cbc = 1.67pF. But that doesn't change the conclusion about the Miller approximation anyway.
– G36
Jul 12 at 18:35
• @G36 Oh, nothing against Miller, just that the intrinsic capacitances change with polarization, unless the capacitances, themselves, are meant to be fixed (which I can't really tell from the OP). Jul 12 at 20:55
• Does an Rbc resistor (something as 100k-10 Meg) change something? Jul 13 at 7:57

Cbc + Cbe = 3.6 pF is in parallel with Cco=1 pF , net 4.6 pF with load reduces to ;

Req=1419, Ceq =5.6 pF f(-3dB)=20.02 MHz might be closer to textbook

EE&O

My simulator gives this result, a "little" different behavior.
So I searched different functions ( Vo versus {Vb, Vg, V2}). For reference, here are two pictures with the use of a CCCS (linear).
Note the influence of the Ccb and Ceb capacitor.  • Thanks for simulating! Q1, that's a stock model, not the stripped-down/basic model OP used, right? Can you adjust relevant parameters (TF/TR, C's, RB?) to reproduce OP's cutoffs, and, also demonstrate the C-equivalent version (or alternately, measure the apparent capacitances under bias)? Jul 11 at 11:17
• Changing parameters is not so easy. I am trying an equivalent linear ac model where I can add some capacitors and can evaluate (for now) the Voltage gain function Av=Vc/Vb (under MAPLE). Jul 11 at 13:58
• Oh sheesh, so, even more basic, and symbolic at that. Adventurous. Won't that be a difficult way to reproduce the OP's model, though? (Done in LTSpice if I'm not mistaken.) Jul 11 at 14:43
• Nice demonstration of pole-zero cancellation in the last one! Jul 12 at 15:30
• Yes. Pole/zero around 20 MHz (Vo)/V2). FACT analysis would be great. Jul 13 at 7:27

It's almost as though the simulation is only taking into account Cwo (1pF) and ignoring Cbc and Cce in its determination of a value for Co..

Try running a simulation with Cwo removed and see if that highest frequency pole disappears altogether.

• "It's almost as though the simulation is only taking into account..." Interesting idea, but how could you prove that's what's going on? Simulations don't just drop elements. Granted, that you can enter ESR/ESL separately (hidden fields!) in LTSpice, maybe the literal schematic doesn't match the simulation. Jul 11 at 14:44
• @TimWilliams I don't know how to answer that. Have you any ideas? Jul 11 at 14:49