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I was trying to find out what parameters affects propagation delay and how. When trying to discover if somehow the propagation delay could increase with the increment in the amount of inputs in a gate, I found this paragraph in section 5.7.1 of INTRODUCTION TO DIGITAL SYSTEMS by Mouhammed Ferdjallah:

"The fan-in is the number of inputs of a logic gate. For examples, a two-input AND gate has a fan-in of 2 and a three-input NAND gate has a fan-in of 3. (...) If the number of inputs is increased, the parasitic capacitance and thus the propagation delay is increased and the noise margin is lowered. Normally, the propagation delay increases as a quadratic function of the fan-in."

I'm trying to:

  1. Find other sources that confirm that the number of inputs in a logic gate increases its propagation delay following a quadratic function.
  2. Understand why do the parasitic capacitance increase. In a CMOS NAND gate, no matter how many inputs you have, each input drives only two transistors, one PMOS and one NMOS (in the book this section is just after the "CMOS Logic Networks" section).
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  • \$\begingroup\$ That is not borne out for two common gates (both from a single manufacturer so we compare apples with apples). SN74AC00 (quad dual input nand) and SN74AC10 (triple 3 input nand). The 3 input device has lower propagation delay (worst case) than the 2 input device. ti.com/lit/ds/symlink/sn74ac10.pdf and ti.com/lit/ds/scas524e/scas524e.pdf \$\endgroup\$ Commented Jan 20, 2020 at 14:17
  • \$\begingroup\$ It doesn't affect the propagation delay of the gate being fed but rather the whole circuit. The delay is caused externally to the input, not after the input. \$\endgroup\$
    – Transistor
    Commented Jan 20, 2020 at 14:19
  • \$\begingroup\$ I would say the signal prop. delay due to fan-in is the circuit track and gate input capacitance, Ciss is a linear function (T=RC) of Driver RdsOn in CMOS (Zoh,Zol=Vol/Iol) and Ciss of each gate and not a quadratic function. \$\endgroup\$ Commented Jan 20, 2020 at 14:31
  • \$\begingroup\$ It's a quote from subsection "5.7.1 Fan-in and Fan-out Effects" of the section of "5.1 PRACTICAL ASPECTS OF LOGIC GATES". My interest is in the effect on the gate propagation delay. I will edit the question. @PeterSmith, I did this with many logic gates with many manufacturers for a inconsistent result. I'm almost getting to a point were I'll forget what I read in Ferdjallah and consider that the amount of inputs do not affect propagation delay, or its effects are not as simple as a quadratic law, do to lack of better references about how it works. \$\endgroup\$
    – Gabriel T.
    Commented Jan 20, 2020 at 14:34
  • \$\begingroup\$ Been in the ASIC industry for years. I have been breaking my head how that statement could be true. I can't think of anything! The only time the parasitic capacitance is increased is if you connect several inputs together. But in ASIC libraries you would never need to do. If you had an N-input gate you always had an N-1 inputs gate as well (even for the AOI cells). \$\endgroup\$
    – Oldfart
    Commented Jan 20, 2020 at 16:22

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I can only answer in the context of standard CMOS logic gates.

For NOR and NAND gates, as the number of inputs increases you also increase the number of transistors that are connected in series. NAND gates of \$N\$ inputs have \$N\$ NMOS transistors in series while NOR gates have \$N\$ PMOS transistors in series. The series transistors have essentially the same effect as series resistors...they increase the time required to change the voltage on the load capacitance. Now you could increase the width of the series transistors to compensate for this, but that would increase the input capacitance of the gate and just move the problem to the previous logic stage.

Increasing the number of inputs for a NAND or NOR gate also increases the number of transistors that are connected in parallel, with all of their drains connected to the logic gate output. This increases the internal parasitic capacitance of the gate, further exacerbating the slower transition time. More wiring is needed to connect all of these capacitors, so even more parasitic internal capacitance.

So, if the propagation delay is proportional to \$R\times C\$, and increasing the number inputs increases both \$R\$ and \$C\$ then you could argue that the transition time is proportional to \$N^2\$. I don't think the relationship is quite that simple (not precisely \$N^2\$) but it is certainly worse than linear.

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