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3T1C DRAM cell

Could anyone help explain how the above 3T1C DRAM cell works? T means transistor and C means capacitor. Why is reading it not destructive?

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  • \$\begingroup\$ Where does it say a read is not destructive? I suppose it is because you are not actually draining the cap to read its value in this case. Instead you are reading the state of T2's source-drain. Still seems like it might need refreshing occasionally though. \$\endgroup\$ – DKNguyen Jan 20 at 14:38
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    \$\begingroup\$ T3 is connected to the storage capacitor through the gate of T2, which is a very high impedance. No (or very little) current can flow through that gate, so the read operation won't change the state of the capacitor. Changing the capacitor requires you to make a circuit for current to flow through T1. \$\endgroup\$ – user1850479 Jan 20 at 14:40
  • \$\begingroup\$ @user1850479 If the T2 is high impedance, how could the read operation (the read bitline) gets the voltage/data from the storage capacitor? \$\endgroup\$ – smwikipedia Jan 20 at 14:58
  • \$\begingroup\$ @DKNguyen Yes, I think it is reading the voltage between the source and drain of the T2. But how is it related to the voltage presented by the storage capacitor? \$\endgroup\$ – smwikipedia Jan 20 at 15:06
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    \$\begingroup\$ @smwikipedia voltage on the gate turns the transistor on/off, but since this is a mosfet, no current flows through the gate. The capacitor connects/disconnets T3 (and then the bitline) to/from ground, which causes a 1 or 0 to pass down the line. \$\endgroup\$ – user1850479 Jan 20 at 15:44
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During a read T1 is off and T3 is on.

Then T2 controls the read line from the charge on the capacitor. Since it’s gate is very high impedance, no current is drawn from C to do that. That leaves C’s charge, hence the state of the bit, unchanged.

T2 is both the strength and weakness of this cell design. Yes, it makes readout nondestructive. But it also takes up significant space, increasing cost. As system design advanced to handle destructive reads, this design became disfavored.

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  • \$\begingroup\$ I updated my question. Hope it can better reveal the root of my confusions. Could you take a look? Thanks. \$\endgroup\$ – smwikipedia Jan 21 at 7:16
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    \$\begingroup\$ You asked if read was destructive. It’s not. But depending on the type of T2,, the read and write bit lines have opposite logic from each other; one active high and one active low. \$\endgroup\$ – Bob Jacobsen Jan 21 at 7:22
  • \$\begingroup\$ The ADD part may be a bit off topic. I moved it to another thread. electronics.stackexchange.com/questions/477173/… \$\endgroup\$ – smwikipedia Jan 21 at 7:32
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Not sure this is true for all DRAMS, but some do a write following a read (transparent to the user) to restore the charge on the storage cap.

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  • \$\begingroup\$ 3T1C is an old fashioned cell type where reading is nondestructive and so rewriting after read is unnecessary. It isn't used much anymore because it requires extra transistors compared to a conventional cell. \$\endgroup\$ – user1850479 Jan 20 at 14:45

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