I am using PIC18F67K40. When I went through the Errata datasheet I found out that I am using A3 revision Device. There is an item number 5.1
Can somebody explain to me what is the exact meaning of this?
I have added snap below
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This would only affect you if you are using the SMBus. The proper spec is as follow (from the datasheet):
In the errata the actual performance is described:
So it meets the SMBus spec if Vdd is > 4V. If Vdd < 4V (down to 2.7V) it may be as low as 0.7V.
In practice this would likely mean a reduction in noise margin rather than a failure, and only if Vdd < 4V, and only for SMBus inputs.
"Input low voltage threshold level is dependent on VDD."
This means that the microcontroller does not use an internal reference voltage source for Low input signal comparison.
Below there is an example of behavior at VDD = 5V.
In case You power supply voltage change let's say from VDD=5.0V to VDD=4.5V [-16%] the Signal Low area might change aswell from <0 - 0.8>V to <0 - 0.67>V [-16%].