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I have a verilog code that describes a simple RAM. I use Genus synthesis tool to do synthesis, then generate a .sdf file for post-synth simulation. However, The tool generates .sdf file with faulty timingchecks. The setuphold timings are off. Summing setup and hold times yields negative values, which causes failure in sdf backannotation when simulating.

Following is a part of the SDF file,

(CELL
 (CELLTYPE "SDFQD1")
 (INSTANCE memory_bank_reg\[29\]\[1\])
 (DELAY
    (ABSOLUTE
      (PORT CP (::0.0))
      (PORT D (::0.0))
      (PORT SI (::0.0))
      (PORT SE (::0.0))
      (IOPATH CP Q (::-6916) (::-6612))
    )
 )
 (TIMINGCHECK
    (SETUPHOLD (negedge D) (posedge CP) (::11915) (::1925))
    (SETUPHOLD (posedge D) (posedge CP) (::12580) (::-12089))
    (SETUPHOLD (negedge SI) (posedge CP) (::4566) (::6006))
    (SETUPHOLD (posedge SI) (posedge CP) (::15967) (::-18683))
    (SETUPHOLD (negedge SE) (posedge CP) (::12574) (::3588))
    (SETUPHOLD (posedge SE) (posedge CP) (::7001) (::-2850))
 )
)

As you can see, one of the setup hold time is faulty. There are hundreds of errors like this in the file, this is just one of them. I tried different processes (FreePDK, TSMC), but they all yield faulty results.

Following is the verilog code of the RAM,

`timescale 1ns/10ps


module instruction_memory(
clk0, csb0, web0, addr0, din0, dout0);

input clk0, csb0, web0;
input [5:0] addr0;
input [15:0] din0;
output reg [15:0] dout0;

reg [15:0] memory_bank [0:63];

always @(posedge clk0)
begin
    if(!csb0)
    begin
        if(web0)
        begin
            dout0 <= memory_bank[addr0];
        end
        else
        begin
            memory_bank[addr0] <= din0;
        end
    end
end
endmodule 

Finally the synthesis script for Genus,

# Reading Verilog Codes and Elaborating
read_hdl -v2001 {instruction_memory_dff.v}
elaborate instruction_memory

# Defining Time Constraints
create_clock -period 80000 -name clkin1 -domain domain_1 clk0
set_clock_transition -min -rise 100 clkin1                  
set_clock_transition -max -rise 200 clkin1
set_clock_transition -min -fall 100 clkin1
set_clock_transition -max -fall 200 clkin1


set_input_delay -clock clkin1 -clock_rise 500 clk0 web0 din0* csb0 addr0*
set_output_delay -clock clkin1 -clock_rise 500 dout0*

set_driving_cell csb0 web0 addr0* din0* -cell BUFFD6

set_load 5 dout0*

# Synthesizing
set_db operating_conditions NCCOM
set_db syn_generic_effort high
set_db syn_map_effort high
set_db syn_opt_effort high
syn_generic instruction_memory
syn_map instruction_memory
syn_opt instruction_memory


# Writing Report Files
report timing > report_time.txt
report gates > report_gates.txt
report area > report_area.txt

# Writing Design Files
write_hdl instruction_memory -language v2001 > synth_instruction_memory_dff.v
write_sdf -edges check_edge -design instruction_memory > 
instruction_memory_dff.sdf

What might be the problem here? Let me know if I missed some information.

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  • 2
    \$\begingroup\$ @Oldfart The sum of setup and hold times is negative, which is a problem. A negative hold time is fine, but the sum should be positive. \$\endgroup\$ – zeke Jan 21 at 17:28
  • 1
    \$\begingroup\$ You are right I checked the top and bottom one but missed the middle one which is indeed wrong. I'll delete my comment. \$\endgroup\$ – Oldfart Jan 21 at 17:32
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I found the issue. It turns out removing the clock slew (set_clock_transition in the script) solved it, though I'm not exactly sure why. Feel free to explain if you can. Maybe this will help someone else in the future.

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