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I am trying to understand the DRAM working paradigm. I just read this article about interleaved memory. It says:

Interleaved memory results in contiguous reads (which are common both in multimedia and execution of programs) and contiguous writes (which are used frequently when filling storage or communication buffers) actually using each memory bank in turn, instead of using the same one repeatedly. This results in significantly higher memory throughput as each bank has a minimum waiting time between reads and writes.

And...

That way, contiguous memory reads and writes use each memory bank in turn, resulting in higher memory throughput due to reduced waiting for memory banks to become ready for the operations.

My questions are:

  • What prevents a DRAM bank from being ready? Refresh?
  • Why is the throughput significantly higher with interleaving?

My current understanding is:

DRAM needs periodic refresh to keep the stored data, which is the the D stands for. For continuous read/write against a single bank, I can think of that such r/w operations will sooner or later collide with the bank's refresh operation. When that happens, the r/w will have to wait until the refresh is done. If we interleave multiple banks, it is less likely that the collision will happen. So there will be less wait and higher throughout.

But it seems my understanding is not quite relevant to the "waiting time between reads and writes" in the first quote.

Any other reasons?

Thanks.

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This isn't about refresh.

The bus may be running at a higher speed than a single RAM module allows. Then you either need wait states on the bus or interleaved RAM modules, so subsequent accesses —the most common— touch the first module, then the second module, the first again etc. The bus throughput almost doubles, given subsequent reads or writes are common.

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  • \$\begingroup\$ Thanks. So it is to mitigate the speed mismatch between the bus and RAM modules. The r/w requests are issued at the higher bus speed. But the RAM modules can only serve them at a lower speed. So we need multiple modules. It looks like some kind of pipeline? \$\endgroup\$ Jan 22 '20 at 7:04
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    \$\begingroup\$ A functions similar to a pipeline, but this term isn't used as it's still RANDOM access memory. If the accesses are not subsequent, the bus controller automatically inserts waitstates. \$\endgroup\$
    – Janka
    Jan 22 '20 at 7:31

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