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Implement the following circuit:

enter image description here

Note that this is a latch, so a Quartus warning about having inferred a latch is expected.

This is my implementation

module top_module (
input d, 
input ena,
output q);
always @(*)
    begin
        if(ena==1'b1)
            q=d;
        else
            q=q;
    end endmodule

Can someone help me why there is a inferred latch even though i am solving q for every case possible?

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  • \$\begingroup\$ If you are implementing D flip flop, you need a clock. The verilog implementation can be found here, asic-world.com/examples/verilog/d_ff.html. Your implementation is actually a latch. \$\endgroup\$ – X J Jan 22 at 17:41
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It's a latch because you allow q to be updated when ena goes high or any time d changes when ena is high. This is exactly the behavior that describes a latch. This is how you should code a latch if you intentionally want to produce one.

To generate a flip-flop you should make the block triggered by a change in ena (i.e always @(posedge ena)) rather than by any change in the inputs.

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