Implement the following circuit:
Note that this is a latch, so a Quartus warning about having inferred a latch is expected.
This is my implementation
module top_module ( input d, input ena, output q); always @(*) begin if(ena==1'b1) q=d; else q=q; end endmodule
Can someone help me why there is a inferred latch even though i am solving q for every case possible?