This question is mainly to check if I understood i2c protocol and hardware correctly. Because pin modes confusing me a little, ia m jsut a beginner.

  1. I2C SDA and SCL lines are pulled high with pull up resistor. In my case I use 4k resistor.
  2. Master pulls SDA line to ground and starts clocking on SCL line after that, and thats called start condition.
  3. Master send out an adress to slave and r/w bit.

Here is what confuses me.

  1. Master reconfigures the pin SDA in to input mode to recieve ACK bit while slave reconfigures its input pin to output pin and pulls SDA line to ground to send and ACK bit.

And then same repeats with the rest of the bytes untill stop condition is met. The question is, is pin actually reconfigured from output to input on the master to read the ACK bit or there is some other mechanisms that i am not aware of?

From what I read on AVR forums I can do the following: In case my SDA pin is on PB0, to make it high I would switch PB0 to input without internal pull up (leaves it floating). To make pin go low I would set it to output low. While I am input mode I could also read the input from the same pin.

Please correct me if i am wrong.


3 Answers 3


I²C has two states on the SCL/SDA lines. A weak high level, and a strong low level. To achieve that by bit-banging, set the output register to low, and leave it alone later.

Only ever switch the SCL/SDA data direction register between input/weak high level and output/strong low level.

For SCL you have to do the same as for SDA because the slave may choose to pull the SCL line low for clock stretching. You have to release clock, then check if the slave also released it. Not supporting clock stretching properly is a bug even found in professional I²C hosts implemented in hardware.

Most AVR controllers have an I²C host/device controller built in hardware, and it's one of the few which is implemented correctly. You don't have to bitbang I²C on those controllers. Check the datasheet.

  • \$\begingroup\$ a weak high level is when pin is input mode basically, and is left floating (no pull up internal). stong low is when pin is in output mode and pulled to low(grond) via internal cmos transistor ? and yes i am aware of the fact that i have i2c pirephiral :) \$\endgroup\$ Commented Jan 25, 2020 at 9:31
  • \$\begingroup\$ That's correct. \$\endgroup\$
    – Janka
    Commented Jan 25, 2020 at 9:32
  • \$\begingroup\$ thank you so much sir. \$\endgroup\$ Commented Jan 25, 2020 at 9:32

I2C as a standard protocol will have dedicated hardware blocks which will be use for bit timing, and protocol Compliance.

It seems that you are bit banging the I2C protocol manually. For high impedance as you said, making it input with no internal pull-ups and pulldown is fine.

  • I2C is a complex protocol to implement manually and still to accommodate all the necessary features supported

  • If the slave being controllers is simple device (a sensor or a display) it will be easier

  • Multimaster scenario and some known error conditions are challenges will be limitations

  • Please also have a chance to reset the slave if possible

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  • \$\begingroup\$ well i know that there is a peripheral deticated to I2c in my MCU, i just wanted to know how exactly it functions so i can for example implement one my self if needs to. \$\endgroup\$ Commented Jan 25, 2020 at 9:28

Here is a good resource - https://learn.sparkfun.com/tutorials/i2c. There you can see that open-drain outputs (and inputs) are connected in parallel in the so-called wired OR.

I2C hardware

  • \$\begingroup\$ I am aware of open drain, however there is no such mode for AVR mcu that i am working on. this why i asked this question. i have an integrated piripheral that lets me handle i2c but i just wanted to know how can i implement my own \$\endgroup\$ Commented Jan 25, 2020 at 9:35
  • \$\begingroup\$ Of course, the same protocol can be implemented in various ways... but it is a good idea to know how in principle devices are connected to busses... \$\endgroup\$ Commented Jan 25, 2020 at 9:44

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