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I would like to DC bias an AC signal using a voltage divider as shown in the following schematic. I realise the bias point would be subject to noise from the power rails, but that is not a concern for this application.

schematic

simulate this circuit – Schematic created using CircuitLab

I understand that C1 and R2 (and possibly R1?) would form a passive high pass filter. I am familiar with the calculation for a high or low pass filter involving a single capacitor and resistor but am unsure how to proceed when two resistors are used as shown.

Assuming only C1 and R2 were present, the cutoff frequency f = 1 / (2 Pi R C) = 159 Hz. Could you give me a hint what to do next when R1 is included? This is NOT a homework question.

Just for your reference, I have already considered answers to these questions:

Adding a DC bias to an AC signal for amplification and measurement

Biasing an AC voltage for input to ADC

How do I bias an AC signal for sampling?

DC biasing audio signal

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Based on this comment:

"For signals all voltage sources have a resistance of 0 Ohms, so the both resistors are effectively in parallel. – Tom Kuschel 3 mins ago"

would it be correct to redraw the circuit as follows?

schematic

simulate this circuit

The parallel resistance (10K || 10K) could then be calculated as 5K.

f = 1 / (2 Pi 5*10^3 100*10^-9) = 318 Hz

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  • \$\begingroup\$ For AC signals the two resistors are effectively in parallel. \$\endgroup\$ – John D Jan 27 '20 at 20:22
  • \$\begingroup\$ I'm not an expert, but you have both Resistors in parallel for frequency analysis. \$\endgroup\$ – Tom Kuschel Jan 27 '20 at 20:22
  • \$\begingroup\$ John D could you possibly elaborate on the reasoning why they should be considered to be in parallel? I've seen a similar comment elsewhere but it lacked an explanation. I'd be happy to follow a link. \$\endgroup\$ – Pzy Jan 27 '20 at 20:29
  • \$\begingroup\$ For signals all voltage sources have a resistance of 0 Ohms, so the both resistors are effectively in parallel. \$\endgroup\$ – Tom Kuschel Jan 27 '20 at 20:37
  • \$\begingroup\$ @Pzy Just make sure that the \$X_C\$ of the capacitor is small, at the frequency of interest, compared to the parallel combination of \$R_1\mid\mid R_2\$. This will ensure you can "drive" the divider without much signal attenuation. Another way of saying this is that you want your high-frequency cutoff frequency to be at least one decade, or more, below your frequency of interest. Of course, the input impedance of whatever is being driven by your resulting output matters, as well. But that's not specified by you. \$\endgroup\$ – jonk Jan 28 '20 at 7:20
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For AC analysis, you would consider all DC sources to be ground. Then, R1 and R2 are in parallel and your cutoff frequency is 1/(2*pi*R1||R2*C)

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