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I am trying to design an op-amp with a high-pass feedback. The diagram is shown below. The high pass feedback has a corner frequency at 1Hz.

enter image description here

The op-amp itself is two stage as can be seen below.

enter image description here

Based on the books that I have been reading and the number of designs I have found online, the procedure that is generally used involves taking the compensation capacitor into account from the get go. In all of those designs, we assume we want a phase margin > 62 degrees and come up with a value for the compensation capacitor. My question is, how would a high-pass filter in the negative feedback path affect the choice of compensation capacitance needed? In all the designs I've seen, the compensation capacitance was taken to be 0.22*CL (0.22 to meet the phase margin requirements). Should the addition of a high pass filter affect this calculation and if so, how ?

Here is the other question: I have only about 55𝜇A to play with based on the power requirements. In other to meet the required GBW, I need about 17𝜇A in the branch that contains M1 and M3. I would naturally just mirror this current to the branch containing M2 and M4. However, this would the current in this branch 34𝜇A leaving only about 20𝜇A for the second branch which is too little. The second branch should consume the highest amount of current. The only way I can reduce the current in the middle branch is by mirroring only a fraction of 17𝜇A into the branch containing M2 and M4. This makes things very hard because it would implying that M1 and M2 (and also M3 and M4) are no longer of the same sizes. Based on the number of designs I've seen, M1 and M2 (and also M3 and M4) are always of the same sizes. This seems to imply that something is quite wrong. I wouldn't mind some assistance if possible.

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  • \$\begingroup\$ You haven't got a compensation capacitor explicitly shown in any diagram. \$\endgroup\$ – Andy aka Jan 28 '20 at 15:58
  • \$\begingroup\$ Would you mind adding a bit more context to your question? are you designing an ASIC? or are you designing something on a PCB? from the phrase "..it would implying that M1 and M2 (and also M3 and M4) are no longer of the same sizes.." talking about sizes of transistors I would think that you are designing an ASIC and not designing an op-amp circuit on a PCB using off-the-shelf components, am I right? \$\endgroup\$ – Vinzent Jan 28 '20 at 18:24
  • \$\begingroup\$ Unrelated to the original post, but can you share the circuit tikz code for this. Would be really helpful for me. Thanks \$\endgroup\$ – user2757771 Dec 12 '20 at 22:44
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The capacitor across the feedback resistor adds a zero in the loop. That is to say that it increases loop gain but it also adds phase, improving stability. This capacitor also adds a pole at a higher frequency which has the potential to cancel out the stability improvement of the zero. So the capacitor value must be carefully chosen so that the loop gain gets down to unity before this higher frequency pole is reached.

The compensation capacitor's value would be chosen to give the desired phase margin, usually for unity closed loop gain, but maybe for a higher closed loop gain for a decompensated op amp irrespective of how the external circuit is configured. The designer then has the option of including a capacitor across the feedback resistor to further improve stability if desired. This capacitor is sometimes included for the dual purpose of reducing high frequency noise.

EDIT

You can vary the current in both the input and output stages together by varying Ibias. To vary the current in just the input stage insert and vary a resistor between the source of M5 and Vdd.

The current in either side of the input stage should be kept balanced (equal) or distortion will result.

At a simple level of thinking, slewrate is set by the current in the input stage or the current in the output stage, which ever is smaller.This is because it is these currents which charge the compensation capacitor.

For example, if there is 20uA total in the input stage and 35uA in the output stage then the slewrate equals (assuming a 100pF Ccomp) :-

SR = dv/dt = i/C = 20uA/100pF = 0.2V/us

EDIT

Open loop gain is determined by the transconductance, Gm of the input stage and the impedance of the compensation capacitor at any particular frequency.

O.L Gain = Gm.Xc

Gm does decrease as the input stage’s differential amp’s tail current decreases, but this shouldn’t reduce GBW because as Gm decreases (due to reduced tail current) you would decrease the size of the compensation capacitor (increasing the O.L gain back up) to achieve the desired phase margin of somewhere between 45° and 65°.

EDIT

That op amp design could do with an output stage on it:

FET OP AMP WITH OUTPUT STAGE

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