Before detailing my answer, I want to stress the fact that we are dealing with large signal circuits, therefore it is no more possible to model the MOSFET as a simple voltage controlled current generator with the capacity of sourcing and sinking any amount of current: in this context, its behavior is more similar to a switch that sinks current from a terminal (the drain \$D\$, since we are dealing with a \$n\$-channel MOSFET) and sources the (nearly) same current from the other one (the source \$S\$). That said, let's go answer each single question.
1) why does the source voltage have that behavior? It seems the behavior of the voltage across a capacitor after a rectifier diode (in fact, a simple capacitance cannot determine that profile, which is typical of an envelope detector, starting from a sinusoidal signal).
Because its behavior is almost exactly the same of a peak rectifier (diode+capacitor) since also in this circuit you have an active device (the MOSFET), which charges a capacitor, which in turn is a posteriori discharged by some sort of load (the bias current generator) in a periodic process.
To understand why it is so, let's analyze the circuit behavior in detail: let \$T=2\pi/\omega\$ be the period of the sinusoidal input gate voltage \$V_{G}(t)=V_1\cos\omega t\$. Starting from \$t=0\$ (but assuming the circuit is working from \$t=-\infty\$ in order to neglect turn-on transients), the circuit evolves according to the following phases:
- After the MOSFET gate voltage has reached its maximum value \$V_{G_\mathrm{max}}=V_1\$, it starts to decrease and rapidly while the source voltage \$V_S\simeq V_1-V_\mathrm{threshold}\$ is kept nearly constant by the large charge stored in the capacitor \$C\$. This causes \$V_{GS}\$ to fall below the \$V_\mathrm{threshold}\$, interrupting the capacitor charging process started a preceding time, causing the vanishing of the drain current \$i_\mathrm{D}\$.
- When \$i_\mathrm{D}=0\$, \$V_S\$ starts to decrease linearly in time \$t\$ towards \$V_{SS}\$, since the capacitor starts to be discharged by the constant current generator \$I_\mathrm{BIAS}\$ at a rate
$$
\frac{\mathrm{d}V_S}{\mathrm{d}t}=-\frac{I_\mathrm{BIAS}}{C}\iff V_{S}(t)= V_1-V_\mathrm{threshold}-\frac{I_\mathrm{BIAS}}{C}t
$$
- The gate voltage, after reaching its minimum value \$V_{G_\mathrm{min}}=-V_1\$, rises again and when
$$
\begin{split}
V_{GS}=V_G(t)-V_S(t)= V_1\cos\omega t&-V_1+V_\mathrm{threshold} + \frac{I_\mathrm{BIAS}}{C}t =V_\mathrm{threshold},\\
&\Updownarrow\\
V_1\cos\omega t-V_1&+ \frac{I_\mathrm{BIAS}}{C}t=0
\end{split}\label{1}\tag{1}
$$
the MOSFET turns on and starts to charge the capacitor \$C\$ by a current \$i_\mathrm{D}-I_\mathrm{BIAS}\$, until \$V_{G_\mathrm{max}}\$ reach its maximum value at \$t=T\$. After that the circuit behaves by repeating the for steps describes above, in a periodic mood.
Edit. The maximum source voltage is \$V_S\simeq V_1-V_\mathrm{threshold}\$ since the charging of the capacitor stops when \$V_{GS}=V_G(t)-V_S(t)=V_\mathrm{threshold}\$. This makes also formula \eqref{2} below independent from the characteristics of the MOSFET. I guess this is a nice trick that could be used in the design of circuits.
2) how do we choose the value of the capacitance? Should it be high or low?
Let \$t_p\$ the pulse width of the current peaks you want to produce from your sinusoidal input. By formula \eqref{1} above written for \$t=T-t_p\$ we have
$$
V_1\cos\omega (T-t_p)-V_1+\frac{I_\mathrm{BIAS}}{C}(T-t_p)=0.\label{2}\tag{2}
$$
Thus we formally get
$$
C=\frac{I_\mathrm{BIAS}\left(1-\frac{t_p}{T}\right)}{V_1\left[1-\cos2\pi\left(1-\frac{t_p}{T}\right)\right]}T
$$
The parameter \$t_p/T\$ can be interpreted as a sort of duty cycle.
3) I have seen many circuits with a source capacitance, which was used as a bypass capacitance. Its aim was that of bypassing an additional source resistance (inserted in order to make the transistor more stable to some fluctuations of the working point), since that resistance determines a gain lowering.
From a circuital point of view, this last circuit (with a bypass capacitance) is identical to that seen now. But I have never heard that a Common Source Amplifier with bypass capacitance keeps the transistor ON only for a brief time and determines short drain current pulses. So there must be a basic difference between these 2 kinds of circuits (maybe on the value of the capacitance?).
As you guessed, it is (as always) a matter of circuit design. By looking at equation \eqref{2} above, it appears clearly that it cannot be satisfied by arbitrary values of \$I_\mathrm{BIAS}, V_1, t_p\$ and \$C\$. For example, low values of \$C\$ and \$V_1\$ can cause the MOSFET remaining on for all \$t\$: in this case, the output voltage \$V_S\$ follows quite faithfully the time behavior of the voltage \$V_G\$. The instructive and nice paper of Alex Rysin on the behavior of the emitter follower at various regimes [1] could give further insight, even in the standard, classical case when there is a source (emitter) bias resistor instead of a bias current generator.
[1] Rysin, Alex, "Avoid Clipping in Emitter Follower with AC-Coupled Resistive Load", Electronic Design,
March 17, 2015.
