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I'm working on a data collection/testing setup for multiple pogo pin test PCBs (~10 max per master) connected over I2C, daisy chained together. The design is based around the AD5593R ADC/DAC/GPIO chip, which unfortunately has only one bit to change the I2C address.

Therefore, each board will have an AD5593R and a LTC4316 I2C address translator, plus some unique resistor value for modifying the I2C address.

Is it correct that I won't have to worry about capacitance on the I2C line since the signal will be passing through each translator? Should I choose my I2C pullups based on just the capacitance between each board?

I am using 1 meter long shielded cables to connect each board. Does this design warrant a differential transceiver?

I understand this design is a bit convoluted, but this is a specific one-off test setup where cost/number of chips isn't really important.

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No that will not buffer. Look at the block diagram on pg 6.

enter image description here

It is virtually a complete pass through for SCL/SDA with nothing to isolate and then repeat the signal for both lines nor both sides of each line. It does have the capability to isolate both lines, but definitely no capability to re-drive the signal. The only drive capability that exists is to pull the line low on SDA line only (in order to modify the address).

Interesting IC and the way it intercepts and middle-man-attacks the address. When intercepting and modifying the address, N3 can always override any pull-up to change a HI to a LO, but in order to change a LO to a HI the pull-down drivers on the bus side (left-side) need to be taken out of the picture so that's where N2 comes in. It just completely disconnects the device-side SDA line from the bus so that N3 and the pull-ups on the device side have complete control over the device's SDA line. Then that XOR detects if the incoming address matches the address to be modified. Any address bit that matches gets modified accordingly by the AND gate and injected into the SDA, and any address bit that does not match is forced to zero by the AND gate. The result is either the modified address gets put on the SDA line or some garbled nonsense address which is just be ignored by the device.

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    \$\begingroup\$ +1. The 4-terminal mosfet with the body grounded allows bidirectional isolation. Not commonly seen outside of ICs. \$\endgroup\$ Jan 30, 2020 at 17:22
  • \$\begingroup\$ Very interesting, thanks for the answer. I figured the chip would clock the address into a buffer and re-drive the output, obviously didn't look close enough. \$\endgroup\$
    – sealj553
    Jan 30, 2020 at 17:58
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You may want to check I²C multiplexers instead of address translators.

You can use e.g. a single PCA9548 to split one I²C bus into eight, each of those can have two of your ADCs on it. There's some extra programming needed to control the bus selection logic inside the PCA9548 through I²C. Up to eight PCA9548 may be connected in parallel to the host bus, they have three address pins. No need for chaining them.

If your host platform is Linux, the I²C drivers handle all this automatically. You are presented nine (or more) buses instead of one.

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