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Does anyone knows internal structure of a typical Fast Ethernet 100BASE-TX transmitter? I wonder how MLT-3 voltage levels are formed and what can cause abnormal voltage levels at the PHY output? Thank you.

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Assuming differential lines, the levels are simply strong outputs pulling the wires apart, in either polarity. Or, like CAN, providing no drive at all, for that 3rd level.

problems? reflections.

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    \$\begingroup\$ No, the outputs need to be impedance controlled for all levels. \$\endgroup\$ – Simon Richter Jan 31 at 16:26
  • \$\begingroup\$ Hello analogsystemsrf. Thank you for your answer. Some of the MDI ports are malfunctioning (failing to establish link) and I see abnormal voltage levels on these ports: link pulses around 3.0V instead of normal 1.8V. \$\endgroup\$ – Anton Gorodetsky Feb 2 at 16:47
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PHY chip output stages vary; some have only current sink on/off output, some have multiple current levels. Different output stages may require different transformer setup, but typically transformer center tap is connected to a bias supply, but some output stages can work without. As the output stage uses current sinks, it means that it is high impedance outout and thus the termination and biasing is done with 50 ohm resistors to a bias supply. Some PHYs have selectable modes, so for example it may need to be set to a certain mode in order to work with capacitive coupling between two PHYs without any transformers, and some PHYs may not be compatible with this.

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