Does anyone knows internal structure of a typical Fast Ethernet 100BASE-TX transmitter? I wonder how MLT-3 voltage levels are formed and what can cause abnormal voltage levels at the PHY output? Thank you.
PHY chip output stages vary; some have only current sink on/off output, some have multiple current levels. Different output stages may require different transformer setup, but typically transformer center tap is connected to a bias supply, but some output stages can work without. As the output stage uses current sinks, it means that it is high impedance outout and thus the termination and biasing is done with 50 ohm resistors to a bias supply. Some PHYs have selectable modes, so for example it may need to be set to a certain mode in order to work with capacitive coupling between two PHYs without any transformers, and some PHYs may not be compatible with this.