I'm really desperate right now. I have written a VHDL code that gets an input of type std_logic_vector(0 downto 0) [in__con1_dio4_rs485_rs] which it should collect in 8-bit blocks. For this I use an 8 bit vector [tmp], whereupon I perform a left-shift.
My problem here is that I only need every 8th result of tmp for the output, i.e. always when the vector has been completely rewritten with the inputs. Therefore I wrote a simple if-statement, which passes the tmp-value to the output [Whole-Frame] using the signal cntclk, which counts the passes of the overlying if-statement.
Unfortunately, it does not work if I check the cntclk for 7 (8 bits), because then the value is passed correctly at the beginning, but not anymore. But if I set cntclk to other values, like in the attached pictures, to 7 bits or 9 bits, it works fine.
I'm sorry if it should be a trivial question, but I've been looking for a solution since last week and can't find the right way.
Here the code:
LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.NUMERIC_STD.ALL; USE IEEE.MATH_REAL.ALL; ENTITY User IS PORT ( Whole_Frame_ch5 : out std_logic_vector(7 downto 0) := (others => '0'); in_con1_dio3 : IN std_logic_vector(0 DOWNTO 0); -- SCLK in_con1_dio4_rs485_rx : IN std_logic_vector(0 DOWNTO 0); --MOSI in_con1_dio6 : IN std_logic_vector(0 DOWNTO 0); --CS ); END; ARCHITECTURE rtl OF User IS signal clkT : std_logic := '0'; --clock signal tmp: std_logic_vector(7 downto 0); signal cntclk : integer := 0; BEGIN clkT <= in_con1_dio3(0); PROCESS(clkT) BEGIN if falling_edge(clkT) and in_con1_dio6(0) = '0' then --left shift 8 bit vector tmp(0) <= in_con1_dio4_rs485_rx(0); for i in 1 to 7 loop tmp(i) <= tmp(i - 1); end loop; cntclk <= cntclk + 1; if cntclk = 8 then --only changed this value for screenshots whole_Frame_ch5 <= tmp; cntclk <= 0; end if; end if; END PROCESS; END ARCHITECTURE rtl; -- of User
Screenshots: the output is the second last wave, cntclk the last wave
- Screenshot: cntclk = 6 --> passes tmp to output after 7 shifts
- Screenshot: cntclk = 7 --> passes tmp to output after 8 shifts --does not work
- Screenshot: cntclk = 8 --> passes tmp to output after 9 shifts
The only thing I have changed between these screenshots of the simulation was the value for the if-statement that checks the cntclk.
Thank you in advance..