I'm trying to implement the RiSC-16 (not RISC) processor documented here using Verilog. The processor is really simple, however there is a problem when you try to perform ADD instructions consecutively on a register, for example
add r1,r1,r1 add r2,r2,r2
Looking at the sequential implementation here, this code won't work. Here is why: Since write enable of register file is on throughout the execution, the result of the first instruction gets overridden at the beginning of the second instruction. This is because the target address does not change immediately at the beginning of the next instruction cycle.
Is there a way to prevent this from happening?