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I'm trying to implement the RiSC-16 (not RISC) processor documented here using Verilog. The processor is really simple, however there is a problem when you try to perform ADD instructions consecutively on a register, for example

add r1,r1,r1
add r2,r2,r2

Looking at the sequential implementation here, this code won't work. Here is why: Since write enable of register file is on throughout the execution, the result of the first instruction gets overridden at the beginning of the second instruction. This is because the target address does not change immediately at the beginning of the next instruction cycle.

Is there a way to prevent this from happening?

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  • \$\begingroup\$ Does the register file write "constantly" when WE is asserted? Or does it only write on the clock signal? If it only writes on the clock signal, then you might not have a problem. \$\endgroup\$ – user253751 Feb 7 at 10:34
  • \$\begingroup\$ @user253751 Register file writes on rising edge of clock when WE is asserted. So, it's both. \$\endgroup\$ – zeke Feb 7 at 14:14
  • \$\begingroup\$ Then what is the problem? The target address doesn't change immediately, but it changes before the rising edge of the clock, so the register file writes the new address and not the old one. \$\endgroup\$ – user253751 Feb 7 at 15:27
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RISC-16 is RISC. All RISC CPUs are RISC. Well, your example is one that would never happen in real machine. It is a nonsense. The problem may lie in the pipeline, the RISC tends to execute all instructions in the same amount of instruction cycles, composed by fetch, decode, execute. The pipeline was introduced to speed up the processor: first problem is that all instructions shall have the same the same instruction cycles in order to take the advantage of the pipeline, next it is strictly forbidden to execute a commands that will access and change the value of the same register within one instruction cycle, as the pipeline would messs up.

The only way to reproduce your behaviour, is to intentionally write those assembler codes, as no compiler would do that. If you do program on low level, you should be aware of pipeline and its restrictions.

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  • \$\begingroup\$ RiSC stands for "Ridiculously Simple Computer", so it's not exactly RISC. Also, there is no pipeline in this processor. I suggest you to take a look at the documentations I linked in the original post. \$\endgroup\$ – zeke Feb 4 at 22:46
  • \$\begingroup\$ @zeke No, RISC stands for Reduced Instruction Set Computer. Anyone who tries to change that definition arbitrarily will cause the kind of confusion that you are now suffering. \$\endgroup\$ – Elliot Alderson Feb 4 at 23:12
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    \$\begingroup\$ @ElliotAlderson It literally says that in the documentation of the processor. I know what RISC is, this processor is just named RiSC. \$\endgroup\$ – zeke Feb 4 at 23:15
  • \$\begingroup\$ @zeke How many those processors actually exist? You do really think you'll get an answer for a specific CPU that nobody has and will never have? \$\endgroup\$ – Marko Buršič Feb 5 at 12:13
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'm trying to implement...

You do not say HOW your are trying to implement the processor. Is this in software or hardware?

In case of the latter, what your are describing is a know issue.
It does not only happens in the case of

add r1,r1,r1

But also if you do:

add r1,r2,r3
add r4,r1,r2

The second instruction is using r1 which is still in the pipeline of being changed. (Note that instruction sequences like the one above are perfectly valid to come out of a compiler.)

The solution for it is also well know it is called register folding.
There is a special circuit which checks if the destination register is also in the pipeline for the source. If so a separate feed-back mux provides a copy of the data (which is somewhere forward in the pipeline).

When I am back at home I'll see if I can find a picture of the RISC processor I developed for fun.

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  • \$\begingroup\$ I'm using Verilog to implement this on hardware based on the sequential implementation that is documented. \$\endgroup\$ – zeke Feb 6 at 12:43
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I solved this by doing writing and extracting the new instruction on the same rising edge. Used to be, these two operations would happen on two consecutive rising edges, now they happen simultaneously.

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