# VHDL if statement doesn't work

I've got the next simple VHDL process where I'm checking if an input is 1 and then change a status LEDS:

   LEDSTATUS: process(clk)
begin
if(clk'event and clk = '1') then
if (lp_good = '1') then
stat_led  <= '1';
stat_led2  <= '0';
end if ;
end if;
end process;


I checked physically on the board and the lp_good signal is 0, but it changes the status of the LEDS. If I change to check if 0 (if(lp_good = '0')) still executing the if statement.

Any ideas what I'm missing or is wrong?

• Maybe the led status at startup is set this way. Did you try to add a else statement to "reset" the led status? – PierreOlivier Feb 5 at 11:22
• @PierreOlivier thanks for your answer, I tried it and if I add an 'else' statement to set to 0 the LEDS it does work fine, and this confuse me even more...as far as I know the if statement should work without the 'else' condition, any idea why it works like that? – joe Feb 5 at 11:41
• Check you synthesis result. Without reset your status leds might be optimized to static 1 and 0 values. Thus even the registers will be missing. – Oldfart Feb 5 at 11:41
• No it's to longer executing the IF statement. So it WOULD execute the "else" ... if there was one. Useful search term : "inferred latch" or "inferred register". – Brian Drummond Feb 5 at 11:57
• Maybe lp_good is first 1 and then 0. Or vice versa. As long as it's 1 at some point then the LEDs get changed. – user253751 Feb 5 at 12:23

The problem with your code is that there is no 'alternative'.

What should the hardware do if lp_good='0'? You have not specified that.
In simulation the VHDL simulator will at startup assign a value of 'U' (unknown). If lp_good stays at '0' the value of 'U' remains, but that does not exist in hardware.

Thus as far as the synthesis tool knows the stat_led output should become 1 and never changes. There is no reset value thus it optimizes it to always '1'. You get an output port where the input is connected to the VCC.

I happened to have a Verilog design open and used the equivalent of your code:

always @(posedge sys_clk)
begin
if (eoln==1'b1)
begin
stat_led <= 1'b1;
stat_led2 <= 1'b0;
end
...


This is what comes out:

• I upvoted anyway, but In simulation the VHDL simulator will assign a value of 'U' (unknown) is at best midleading; it might start off as 'U', but the wording implies an assignment to 'U' when lp_good='0', which of course will not happen. – scary_jeff Feb 7 at 16:00