In synchronised circuit, if output of first IC is connected to input of second, should I bother about setup delay or will it work just fine?

If not then what about longer chain? When will be an issue and can I just run circuit on slower clock and it will work again?

  • \$\begingroup\$ Use alternate edges of the clock to avoid problems. \$\endgroup\$
    – Andy aka
    Feb 5, 2020 at 11:39
  • \$\begingroup\$ What if I need bidirectional link? \$\endgroup\$
    – Konidem
    Feb 5, 2020 at 11:41
  • \$\begingroup\$ Use the same principle. \$\endgroup\$
    – Andy aka
    Feb 5, 2020 at 11:55
  • 2
    \$\begingroup\$ Between ICs yes you need to check setup and hold times, clock to output min/max delays, are all compatible with your clock period. \$\endgroup\$
    – user16324
    Feb 5, 2020 at 11:55
  • \$\begingroup\$ @Andyaka In my experience, alternating clock edges avoids hold violations but makes setup problems worse. Can you elaborate on this? \$\endgroup\$ Feb 5, 2020 at 14:10

2 Answers 2


If your clock period is long compared to other delays in your circuit, parameters like setup times have no effect on circuit operation.

But in the more general case, no, you can't ignore setup parameters. Neither can you ignore other timing parameters such as hold time, clk->out delay, or combinatorial delay between clock elements.

Lets look at a simple example - two devices (flip flops or registers) clocked on the same clock edge, with some combinatorial logic in between.

Assume your clock period is Tclk; the clock to output delay is Tclk-q; the prop time through any intervening logic Tprop, and the setup time of the receiving clocked device is Tsu.

You want (Tclk-q + Tprop + Tsu) < (0.80*Tclk). The 0.80 factor is to give you some margin.

If you're designing with FPGAs, the FPGA tool set will tell you if you have a potential timing violation, given your specified clock rate (period). If you're designing with old fashioned discrete logic, you have to do that analysis yourself.


Here's a simple diagram to go along with the above:

enter image description here


When you are connecting two ICs together you usually have much greater clock-to-output and input setup time specifications to deal with, because of the buffers that are added to output and input pins. So, yes you need to do the analysis, using the propagation delay values and setup time values given in the respective datasheets. If there is any clock skew between the two devices then you need to account for that as well.


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