I have a basic question about the simplest PLL scheme:
The purpose of this scheme is that of generating a signal which is a perfect copy of the input signal (which comes for instance from a crystal oscillator). The reference input signal and the output signal will have the same frequency and the same instant phase, at steady state condition.
But I have a question. At steady state condition Vo and Vi are synchronized (i.e. they have same instant phase): the output of the phase comparator will be therefore a constant voltage (that's corresponding to 0 phase error at its input), and so the VCO will generate a stable fixed frequency, equal to that of Vi.
Now, suppose Vi has frequency f1. Then, Vo will be at frequency f1 with 0 phase error with Vi.
Suppose now Vi has frequency f2. Vo will be at frequency f2 with 0 phase error with Vi.
But since in both cases phase error is 0, the constant voltage output of the phase comparator is the same in both cases. How can a same voltage value make the VCO oscillate a different frequencies in those two situations (f1, f2)?