# Phase Comparator and VCO in PLL

I have a basic question about the simplest PLL scheme:

The purpose of this scheme is that of generating a signal which is a perfect copy of the input signal (which comes for instance from a crystal oscillator). The reference input signal and the output signal will have the same frequency and the same instant phase, at steady state condition.

But I have a question. At steady state condition Vo and Vi are synchronized (i.e. they have same instant phase): the output of the phase comparator will be therefore a constant voltage (that's corresponding to 0 phase error at its input), and so the VCO will generate a stable fixed frequency, equal to that of Vi.

Now, suppose Vi has frequency f1. Then, Vo will be at frequency f1 with 0 phase error with Vi.

Suppose now Vi has frequency f2. Vo will be at frequency f2 with 0 phase error with Vi.

But since in both cases phase error is 0, the constant voltage output of the phase comparator is the same in both cases. How can a same voltage value make the VCO oscillate a different frequencies in those two situations (f1, f2)?

• The output of the PLL may be a better source than the original. If there is jitter in the source signal the low-pass filter characteristic in the feedback loop can reduce the jitter. That means there will be a high frequency error signal. Commented Feb 7, 2020 at 12:54

The output of the phase comparator is the same : the output of the "loop filter" is not.

To achieve zero phase error, you need infinite gain at zero frequency; i.e. a component of the loop filter is an integrator.

An easier way to think of the loop filter, in this case, is as a PI controller, with the P (Proportional) term providing fast tracking of phase variations, and the I (Integral) term eliminating phase error.

The P term alone would leave some residual phase error, which multiplied by the "P gain", would provide the DC voltage required to drive the VCO.

EDIT to preserve OP's quote from comments...

At steady state condition the phase error is 0, but that value enters an integrator. An integrator saturates at DC but in this case its input value is not simply DC, it is 0. Therefore, its output value will be the initial value (vout = v(t0) + integral(0 × dt) = v(t0), where t0 is the instant in which lock is reached). So, in cases f1 and f2, v(t0) is different because of their different story, so a different value will drive the VCO.

Yes.

• So is the reason simply the fact that the loop gain is function of frequency? So the VCO receives different control voltages when f = f1 and f = f2? Commented Feb 7, 2020 at 12:48
• You've misplaced cause and effect in that comment. The VCO generates different frequencies f1 and f2 for input voltages v1 and v2. That's what a VCO does. Thus to meet the conditions in your question, the VCO must be fed V1 or V2. Thus the loop filter must generate them.
– user16324
Commented Feb 7, 2020 at 13:34
• But why is the output of the loop filter different, with same input (coming from the phase comparator)? I have a probpem on understanding this concept Commented Feb 7, 2020 at 13:50
• Maybe I got it. At steady state condition the phase error is 0, but that value enters an integrator. An integrator saturates at DC but in this case its input value is not simply DC, it is 0. Therefore, its output value will be the initial value (vout = v(t0) + integral(0 × dt) = v(t0), where t0 is the instant in which lock is reached). So, in cases f1 and f2, v(t0) is different because of their different story, so a different value will drive the VCO. Correct? Commented Feb 9, 2020 at 1:20
• With no memory, your PI controller is a P controller. The loop will lock with a constant (non 0) phase error such that (Error * P Gain) gives the correct control voltage. That "works" because its definition of "work" permits a finite phase error.
– user16324
Commented Feb 9, 2020 at 13:17

If you are familiar with the question 'an opamp has zero voltage between the input pins, so how can it produce an output?', then you have the answer.

A PLL is a feedback system, with infinite gain at DC, large gain well below the loop bandwidth, gains around unity around the loop bandwidth (in fact unity gain defines the loop bandwidth, the loop filter doesn't!), and attenuation well above the loop bandwidth.

At frequencies above DC, the gain is finite, so there will always be some phase error, however small. With a well specified and designed loop, that phase error will be within your specifications.

• So in practice there will always be a finite phase error (very small), which is different in both situations? For instance, 0.01 deg for f1 and 0.02deg for f2, and so there will be a different control voltage for the VCO? Commented Feb 8, 2020 at 19:29
• If there's an integrator in the loop filter, then the PSD output can be mean zero, with an arbitrary output from the integrator. Commented Feb 8, 2020 at 20:42