# What is the typical delay relative to to the maximum delay?

I have a board with a number of ICs, an FPGA, and some flash and RAM devices. The board is designed based on worst case conditions, as it should be. The critical combinatoric path has a maximum delay of 100 ns (as an example).

A few number of these boards are to be used in the laboratory for an application where it is required the that actual combinatoric latency is shorter than 100 ns.

The conditions for the boards running in laboratory are expected to be typical device process, typical supply voltage, and room temperatur (ambient).

What can be expected as typical delay of the combinatoric path, relative to the maximum delay?

I know there will not be an exact answer, but maybe there is some rule-of-thumb for what to expect.

Update: For a start I looked into delay for 7483 and 7496 where there was some datasheet showing both maximum and typical delay, and the typical delay for these range from 55% to 75% of the maximum delay. I think at least it quantifies the area to expect.

• Is the maximum delay constrained by the transistors or the wiring delays? What will be the temperature and supply voltage variation in your laboratory, in relation to the variation used to formulate the maximum delay specification? How risky is a failure? Can you detect when a board is not working properly? Feb 7, 2020 at 14:11
• I know you're hoping for some fast broad guidance in answer to a broad question but it really will depend on the specifics of what you've got and what it's trying to do. You need to greatly expand your question and show the full schematic of the path in question. Feb 7, 2020 at 14:13
• When you say "worst case conditions": 1) What temperature range did you use (commercial, industrial, mil)?; 2) What Vcc (or supply voltage) did you use? 3) For the FPGAs, did you have delays under the "weak, slow" and "strong, fast" corner cases? Feb 7, 2020 at 14:32
• @SteveSh: See your point; the max timing is based on automotive rating devices, so that should give a wider span to typical delay when running at room temperature. Feb 7, 2020 at 14:54
• @EquipDev: If you take your "75% of max delay" as a limiting case, that means you might expect to be able to run with a clock rate (1/0.75) = 1.333 times faster than worst case scenario. But this is no more than a SWAG. You really need to analyze your worst case delay path. The 75% number might apply to some parts, but others you might need to use 60%. Feb 7, 2020 at 15:04

There is no rule-of-thumb that I am aware of.

First consider what causes variations in parameters:

1. Temperature
2. Voltage
3. Factory Processing
4. Aging


For #1 and #2, if your parts will see a smaller variation than what the datasheet indicates, you can take credit for that.

For #3 and #4, these can often be considered to be random, it is extremely unlikely that all parts on your board will be manufactured with worst case processing, or drift in the same direction with age. The methods to account for these are tedious: RSS (Root-Sum-Squared) analysis or Monte Carlo analysis. A lot of engineering is fun for me, RSS is not.

If you don't need to prove worst case by analysis (company policy or customer), and there are only a few critical paths, then consider measuring the paths on the boards.

The design space is a little more troublesome.

As those Idd_switching current surges all pile up --- randomly, yet repeatably if your system state should repeat --- the VDD will sag because the bypass capacitors become more discharged for that 100 nanoseconds (or 50 or 300) AND the GND rises.

Examine your PCB. Is it 2 layer? I've seen legacy TTL boards "randomly" cause RESET on another (MCU) PCB because of long thin ground traces. Solution was to replace the "long thin trace" with a plane.

• I have not insight into the PCB details, but with complex SMDs mounted on both sides I expect it to be 6 or 8 layer. Feb 7, 2020 at 15:52

If you hoping for better than average prop. delays, consider only 3.6V logic rather than 5.5V logic. For example, 74ALCVxx will be similar to logic speeds in ARM CPUs.

per gate
• Operates From 1.65V to 3.6V
• Max tpd of 3 ns at 3.3V
• ±24-mA Output Drive at 3.3V

As usual with CMOS, it runs slower at lower Vdd and higher temps. Although the voltage may seem counter-intuitive to my initial statement, the reason is higher Vdd logic families need to have higher RdsOn by design to prevent high shoot-thru currents necessary for controlled impedance. e.g. 5.5V logic is ~ 50 Ohm drivers and 3.6V logic uses ~ 25 Ohm logic. for a given pF load, this is what limits the external risetime and internal prop delays.

The lower the max voltage range in a logic family, the lower its gate resistance can be, and the lower the Vt threshold, must be, to function well.

• I think that ship has sailed for the OP... Feb 7, 2020 at 14:22
• Wow… that is a lot of parameters... :-) Feb 7, 2020 at 14:49
• get used to it.... but remember like hFE , Ron or RdsOn has a wide temp tolerance of 50% or so which is the dominating parameter that changes proper delay with temp. as well as the threshold voltage, Vt Feb 7, 2020 at 14:51