# Loop Filter in all digital PLL cutoff?

I am implementing an all digital PLL system on an FPGA using VHDL. Now, I have not yet closed the loop, instead I have modelled a sinwave(simulating an input) at 22kHz and also modelled a cosine wave(simulating the NCO(numerically controlled oscillator)) at 24kHz. This means that I am simulating an sin input with regards to a cosine reference. I am then multiplying them (phase detector) and passing the output through a 25kHz LowPass Filter. I am expecting to see a DC output realted to the error at the input, however I am seeing an oscillatoy reponse. Attached is a screenshot of my work so far.

Any help would be greatly appreciated as I am quite stuck here..

Thanks.

I am expecting to see a DC output realted to the error at the input, however I am seeing an oscillatoy reponse.

How can you expect anything but an oscillatory response? $$\\cos(\omega_1 t) \cos(\omega_2 t) = \frac{1}{2}\left ( \cos((\omega_1 - \omega_2)t) + \cos((\omega_1 + \omega_2)t) \right)\$$; you're seeing the low-frequency part of that.

Typically, for that type of phase detector, you do your small-signal analysis assuming that the loop is already in lock, with only small disturbances in phase or frequency. If you model your incoming signal as $$\\cos(\omega t + \phi_1)\$$ and your reference signal as $$\\cos(\omega t + \pi/2 + \phi_2)\$$, then if you do the high-school trigonometry and just a smidge of second-term Calculus you'll see that for $$\\left |\phi_1 - \phi_2 - \pi/2\right| \ll 1\$$, the output of your phase detector, after filtering, will be approximately equal to $$\\phi_1 - \phi_2\$$.

• I understand, but then how can I feed this oscillatory response of the difference to the NCO which only accepts a frequency number as it's input ? Feb 7, 2020 at 16:33
• First, you would drive a loop filter from your phase detector. Second, at each iteration of your loop you feed the NCO one frequency number. Then on the next iteration you give it another one. So the NCO will initially see an oscillating input. If you've designed your loop filter correctly, and if the frequency offset is not too extreme, the loop will eventually come into lock. Feb 7, 2020 at 21:05
• The output in the diagram is the output of the loop filter.. is that the signal which I have to feed into the NCO ? Feb 8, 2020 at 0:15
• I think you need to find a good tutorial on phase locked loops. "The filter in my loop" doesn't make it a proper loop filter. Generally a proper loop filter may include a low-pass filter, but only as an accessory -- a proper loop filter will implement proportional-integral control on the phase locked loop. Feb 8, 2020 at 3:41

Mixing 22kHz with 24kHz should result in a difference of 2 kHz as you see.

Why do you expect DC? This is only possible using a Phase/Frequency Detector using logic called a Type II mixer.

• Because I want that output to feed the NCO when I close the loop and thus need a DC value. Feb 7, 2020 at 16:04
• Why do you expect a phase detector to perform a Frequency to voltage conversion? The loop BW must be wide enough to pull worst case offset without too much jitter from carrier so it locks in a few cycles with the right PID gain. Otherwise , you need aType II mixer which has more jitter. Feb 7, 2020 at 16:07
• When I mean DC I mean a constant binary number to feed the NCO. Should I then connect that waveform in the picture directly to the NCO ? Feb 7, 2020 at 16:10
• en.wikipedia.org/wiki/Phase_detector#Phase_frequency_detector Feb 7, 2020 at 16:11
• When I did some research, many people connect a loop filter to this phase detector and in turn connect the output of the loop filter to the NCO. Am I on the right track with this response however ? Feb 7, 2020 at 16:16

That 2 kHz output is the expected phase error; it's unclear why you expected DC.

Now you need the correct gain and frequency response for the loop filter to enable the loop to lock.

A necessary pre-requisite for lock is that there is enough gain to cover the control range of the NCO. So the negative peak of the phase error must result in an input to the NCO which drives it below the input frequency; and the positive peak must result in a control input driving the NCO above the input frequency. Your next step is to ensure that happens.

During the phase error cycle, the NCO can then sweep across the frequency range of interest, giving it at least a chance to lock. Then you can start to work on the control and stability issues.

• so let me make sure that I am understanding correctly, I just need to multiply the output in the image and then feed it to my NCO ? The code I am using for the NCO is as follows : NCO_Accum : entity work.Accumulator port map ( clk_in => clk_1Mhz, accum_out => LUT_in, freq_int_in => centre_freq ); that was the top_level deceleration Feb 7, 2020 at 18:05
• the entity itself is : Feb 7, 2020 at 18:05
• entity accumulator is port ( clk_in : in std_logic; accum_out : out std_logic_vector(11 downto 0); freq_int_in : std_logic_vector(11 downto 0) ); end accumulator; architecture arch of accumulator is begin process(clk_in) variable cnt : unsigned(11 downto 0); variable i : integer; begin i := to_integer(unsigned(freq_int_in)); if rising_edge(clk_in) then if cnt > 4096 then cnt := (others => '0'); else cnt:= cnt+i; end if; end if; accum_out <= std_logic_vector(cnt); end process; end arch Feb 7, 2020 at 18:05