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I have noticed, in my opinion, some misconceptions in the layout of the majority of DC to DC step-down converters.

I've seen in many PCBs that the trace that goes to the input of the converter (point A) and the trace that goes from the output to the power inductor (point B) are usually too thick. In my opinion it doesn't have to be thicker or same thick as the trace of the output of the power inductor (point C - LC circuit).

The voltage at point A and point B in respect to ground are (usually) the same, so the current is much lower than the output at the trace C.

So, why do many engineers use thicker trace for those nets? Am I missing something?

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Moreover, in many PCBs especially high density boards the power components may be seperated in both sides which I think they should be on the same side. And the input loop should share the same ground path with the output loop. Is that correct?

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    \$\begingroup\$ "why do many engineers use thicker trace for those nets" You might as well...are those thicker traces for Vin and OUT displacing other things? And what happens if your Vin approaches Vout? Your input and output currents will approach each other too. Input current won't be so small compared to output current anymore. "I think they should be on the same side" You speak almost as if space is not a problem on high density PCBs. \$\endgroup\$ – DKNguyen Feb 7 at 21:31
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    \$\begingroup\$ You might want to think about this. You're saying that with a fixed load, the point with a lower voltage will have less current than the point with higher voltage... \$\endgroup\$ – Natsu Kage Feb 7 at 21:34
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    \$\begingroup\$ @NatsuKage He's not saying that. I think he's saying Pin = Pout, so higher voltage in means lower current in. A and B are just separated by a switch. He probably should have used a buck with an external MOSFET. Whereas C is the output with lower voltage, and therefore higher current. \$\endgroup\$ – DKNguyen Feb 7 at 21:35
  • \$\begingroup\$ @DKNguyen You are right, I didn't even think of that! Regarding the high density boards, yes, maybe you would not have another option but how about larger PCBs? \$\endgroup\$ – MrBit Feb 7 at 21:37
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    \$\begingroup\$ @MrBit I think you can make tighter loops if they are on opposite sides of the PCB. Vias aren't the best though. It's also not ideal to have unrelated components on the opposite side which would have high frequency SMPS currents running through their area of the ground plane. \$\endgroup\$ – DKNguyen Feb 7 at 21:38
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Wider traces exhibit less resistance, but more significantly less inductance. The lower resistance and inductance helps a little bit with efficiency, and a little more with ripple, but the larger gains are in EMC. A lower inductance trace radiates less, particularly in conjunction with a solid ground plane.

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  • \$\begingroup\$ And I think that is what I missed... \$\endgroup\$ – MrBit Feb 7 at 21:34
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    \$\begingroup\$ Well the stray inductance of a trace that is in series with a 2uH or 20uH inductor is probably not a concern. \$\endgroup\$ – mkeith Feb 7 at 22:49
  • \$\begingroup\$ True, but you might be surprised how much influence series trace inductance has on the resonance point of a capacitor. And from an EMC standpoint, the trace can radiate more than a shielded inductor with a much larger inductance. \$\endgroup\$ – Cristobol Polychronopolis Feb 10 at 13:19
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Trace at point A carries high di/dt current so it should have low inductance to the decoupling capacitor to minimize voltage spikes.

\$ e = L \frac{di}{dt} \$ and in dc-dc converters di/dt is pretty high so you want to minimize L. A few amps switched in a few ns with a few nH inductance = VIN drops a lot when it switches.

I've had a case where this trace was too long, so when the top FET in the dc-dc turned on, the high di/dt combined with trace inductance created a voltage drop that was large enough to basically crash and reboot the DC-DC chip. So, when output current exceeded a threshold it would hiccup. The fix was to lower the inductance between decoupling cap and dc-dc chip.

Trace at point B is constantly switching between GND and VIN, so its parasitic capacitance to the nearest ground/power planes has to be charged and discharged at every switching. So low parasitic capacitance is best, like a short trace. A copper pour on the switching node would be a bad idea, due to wide area and high capacitance to nearest plane. In this case extra trace inductance doesn't matter since the trace is in series with an inductor anyway...

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