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I’ve designed a 64 bit (16 words * 4-Bits at each location) RAM in logic simulation software, using simple registers. I had to create a 16-to-1, 4-bit wide Mux (no mean feat) in order to ‘select’ one of these registers, and retrieve the 4-bit output. Does this mean larger RAM modules, e.g a 1KB module of say 128 words, and 8-Bits at each location, would need a 128-to-1, 8-bit wide Mux to select the output? This seems insane for larger amounts of RAM, often present on microcontrollers and the like. Is this simply scaled up as you go? e.g. 1MB of 32,768 addressable locations holding 32 bits each, would need a 32,768 to 1 Mux, with each channel a width of 32 bits?

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  • \$\begingroup\$ Insane? Do you know what's insane? Knitting a bunch of knots into rope and using it as memory to run a program on a computer upon which your life depends to send you to the moon. That's insane. \$\endgroup\$
    – DKNguyen
    Feb 8, 2020 at 0:09
  • \$\begingroup\$ That’s not what I asked, but cheers anyway \$\endgroup\$ Feb 8, 2020 at 0:11
  • \$\begingroup\$ My point is lots of stuff is insane in electronics if you just look at the scale. A 32768 mux isn't that much more insane than billions of transistors on a tiny chip. \$\endgroup\$
    – DKNguyen
    Feb 8, 2020 at 0:12
  • \$\begingroup\$ Ok, so do bigger chips absolutely use as many stacked Muxes as required to read the data from each word/address? What I’m really asking is if the operation stays the same but the scale grows. Or is a different method used when dealing with much larger arrays of registers? \$\endgroup\$ Feb 8, 2020 at 0:15
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    \$\begingroup\$ Oh, so you're asking about the specific architecture of the mux used? Because to me, they are all muxes in the same way an adder is an adder no matter how you go about it. You might want to look up row and column decoders. \$\endgroup\$
    – DKNguyen
    Feb 8, 2020 at 0:25

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Yes, but...

Typically RAM is made as a 2D grid, so instead of a 65536:1 mux, you have two 256:1 muxes. One of them selects the row from the grid, and one of them selects the column. The row-select wires and the column-select wires form a grid. Each individual storage bit is only triggered when the row-select and the column-select are both activated at the same time.

Or

Actually, there's only a 256:1 mux, and all 256 bits in that row are activated. There is circuitry at one end of the grid which supports reading and writing 256 bits at a time. When you ask the RAM chip to write 8 bits, it will actually read 256 bits, overwrite 8, then write 256. This is useful with DRAM, since the entire row gets refreshed.

Other combinations are possible, like 512 rows of 128 bits for 65536 bits.

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  • \$\begingroup\$ Yes, but it still uses a crap ton of multiplexers. For a 4GB ram, that's 2 65536:1 MUX. And most computers have more than 4GB. RAM is crazy. \$\endgroup\$ Mar 9, 2020 at 16:11
  • \$\begingroup\$ @TrevorMershon I'm surprised that you're surprised about the 65536 multiplexer lines and not about the 34359738368 individual bits. \$\endgroup\$ Mar 9, 2020 at 16:59
  • \$\begingroup\$ Oh, I am. Imagine now, that you have a 2 PB RAM like in the Summit Supercomputer. That's 9007199254740992 bits. Have fun ;) \$\endgroup\$ Mar 9, 2020 at 17:29
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A multiplexer can be implemented in several ways. You are assuming that the multiplexer is assembled from AND/OR gates (or NAND or NOR) but that is not how the output multiplexer for a memory is made.

These kinds of multiplexers use high-impedance (tristate) drivers onto a common bus. The control logic selects which inputs should be routed to the outputs and enables their drivers. The drivers for all other inputs are placed in a high-impedance state. This kind of design is done at the transistor level, not by wiring up AND and OR gates.

A similar scheme that you could investigate is called "wired-OR" logic.

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