I have been building a synchronized I2C slave receiver with Verilog.
The I2C slave receiver did not encounter any issues when I simulated it with Modelsim. However, it does not function properly when it has been programmed into a (Cyclone V) FPGA.
Below is the waveform from Modelsim simulation:
With the Signal-Tap analyzer on the Quatras program, I have observed two issues on the synchronized counter of the I2C slave. I do not know the root causes of the two issues, please give advice:
Bug #1: Counter number unstable.
Bug #2: Unable to detect input signal(SCK) rising edge.
Here's the Verilog code I used for the counter to detect the SCK rising edge, I have altered the counter to a switch statement as an attempt to fix counter number unstable, but it does not work:
always @(posedge clk) begin if (SCL_buf == 0 && SCL == 1) // posedge SCL begin // Read the Value if(WR_Active == 1) begin // Count Up until Byte Write is completed if(Bit_Count < 8) begin Bit_Count_wr = 7 - Bit_Count; Byte_in[Bit_Count_wr] = SDA; //Bit_Count <= Bit_Count + 1; case(Bit_Count) 4'b0000 : Bit_Count <= 4'b0001; 4'b0001 : Bit_Count <= 4'b0010; 4'b0010 : Bit_Count <= 4'b0011; 4'b0011 : Bit_Count <= 4'b0100; 4'b0100 : Bit_Count <= 4'b0101; 4'b0101 : Bit_Count <= 4'b0110; 4'b0110 : Bit_Count <= 4'b0111; 4'b0111 : Bit_Count <= 4'b1000; endcase end // Acknowledge + Address Check/ Write Byte Process else begin Bit_Count = 0; //........ end end end end SCL_buf <= SCL; end