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I am trying to better understand crystal oscillators. I have been reading ST's AN2867, where they explain that, depending on the crystal, a series resistor (R2 in the diagram below) on the output side should be included to limit the current through the crystal.

This resistor is not something I have seen in most circuits I have encountered. Usually, the crystal, properly loaded, is just directly connected to the oscillator.

So I fired up a simulation, to try and get a feeling for what effects this resistor really has. I modelled the crystal with the usual lumped elements. (I did not choose the values for a specific crystal, I just chose round values, such that the overall performance reasonably matches real-world 8MHz crystals.)

circuit

The source V1 has an amplitude of 2.5V, which I assume is reasonable for a 5V CMOS oscillator (is it not?). R2 is swept from 100 Ohm to 10 kOhm by factors of 2.

simulation

Top panel shows the current sourced by the oscillator. Middle panel is the power through R1, which (I think) should match the power dissipated in the crystal.

What's bothering me is the fact that unless R2 is chosen fairly high (>5k) the power can easily exceed the safe drive level of SMD crystals (100 uW).

At the same time, section 3.5.3 of the app note above suggests that you cannot increase R2 past ~100x R1 without exhausting the gain margin (for the ST oscillators with a transconducatnce of ~10mA/V).

EDIT: (new) The bottom panel shows the phase at the Vout node. @andy-aka mentioned in the comments that the actual oscillations (if any) will occur at the frequency where this phase shift is 180°, which is marked by the solid black line. Clearly, this intercept occurs very close to the parallel resonance frequency (as I should have known). Here the power dissipated in R1 is much lower than at the peak value, but it can still be significant.

What am I missing here? Why do so many circuits omit R2 completely (or choose a low value, <1k), yet do not fry the crystal? For instance in the AVR datasheets, Atmel never mentioned such a resistor. The ST Discovery boards sometimes include a 390 Ohm resistor, sometimes none at all.

Is the output resistance of the inverter sufficient? How can one design for this, other than trial and error?

If it is really that hard to gauge correctly, why don't manufacturers provide better guidance?

I have read many other posts on this site. Two questions in particular are focussed on the series resistor of oscillator circuits. This one focusses on 32 kHz crystals, which are a very different can of worms. 'Selecting a damping resistor for crystal oscillator circuit' has some very interesting answers, but does not address my point of why we see the resistors omitted so often. Please reconsider before marking this as duplicate of either one.

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  • \$\begingroup\$ I think you need to also factor in the phase shift and not assume that the power dissipated occurs at the peak in your graph. \$\endgroup\$ – Andy aka Feb 9 at 12:57
  • \$\begingroup\$ Thanks for the help! Phase shift across the resistor is zero. I assumed the actual oscillation frequency must be somewhere between the (anti-)resonances, where the power is still generally higher than 100 uW. \$\endgroup\$ – polwel Feb 9 at 13:04
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    \$\begingroup\$ You’re using micro cap it seems yes? If so run an ac response showing the phase shift between Vin and Vout. Where it exactly equals 180 degrees, that will be where the oscillator would be naturally running. \$\endgroup\$ – Andy aka Feb 9 at 13:08
  • \$\begingroup\$ I recall struggling to answer the same problem and was not able to pinpoint an exact value for Rs. But the series LC parts do create 1kV each cancelling out 180 deg of phase. tinyurl.com/wl8oc94 Pull the lower charts up and recentre schematic to read better. Turquoise pairs part to graph \$\endgroup\$ – Tony Stewart Sunnyskyguy EE75 Feb 9 at 13:23
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    \$\begingroup\$ @TonyStewartSunnyskyguyEE75 That's one great visualization! Will need to check out closer. \$\endgroup\$ – polwel Feb 9 at 14:01
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If it is really that hard to gauge correctly, why don't manufacturers provide better guidance?

Oscillator designers have a tough job accommodating resonators over a very wide frequency range, and whose power-handling might range from fractions-of-microwatts to milliwatts.

  • The oscillator driver runs in its linear region - a no-no for digital CMOS devices. It may consume significant DC power if its drive strength is large, so CMOS designers are urged to make these devices as feeble as possible, and still oscillate at their high-frequency end, yet still oscillate with low-Z crystals.

  • On top of that, the oscillator inverter might be powered by Vdd that can vary.

  • And on top of that, the end-designer might have more software skills than electrical engineering skills.

In designing the oscillator, one usually errs on the side of over-driving the crystal, because an oscillator that doesn't oscillate is useless, while an overdriven oscillator gives a desired output - perhaps squirrelly, but at least of the desired form (AC rather than DC). A marginally-driven crystal may start up too slowly, causing problems downstream...an overdriven oscillator builds oscillation more promptly.

Is the output resistance of the inverter sufficient? How can one design for this, other than trial and error?

Few inverter spec sheets include \$r_o , g_{fs}\$ that may help tell if oscillations will start. For CMOS inverters, \$r_o\$ is inversely dependent on Vdd, while \$g_{fs}\$ is directly depenedent on Vdd.
74HCU04 swept characteristics from NXP 74HCU04 data sheet
Crystal manufacturers help guide us by specifying load capacitance for their crystals. When a parallel resonant crystal is loaded with this capacitance, and driven with the few volts available from an inverter, crystal current flows roughly in the right ballpark. An added series resistor could be used to adjust drive strength and/or start-up time.
At high frequency, it is recommended that any added series resistor be replaced by a capacitor, whose value is between 0.5X load capacitance, and 1X load capacitance. Especially for 3rd overtone crystals

A good design might run the oscillator much closer to the "starve" point, versus the over-driven point. But doing so risks no oscillation.

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Most MCU datasheets and application notes do list some limits for the crystal, the loading capacitors, or at least they list some oscillator parameters to work with. For instance the STM32 application note you mentioned shows how to calculate if the crystal is compatible or not. If it is not compatible, try another crystal, perhaps with smaller frequency, smaller CL, or smaller ESR. A STM32F100 chip says it can drive the crystal output with a maximum of 1mA.

So in general, selecting a crystal that fits into these limits will just approximately work. The oscillators inside the MCU cannot be simply modeled by CMOS inverter any more, as they can have all kinds of circuitry in them to assist with reliable startup and automatic gain control for the amplitude.

The 100uW drive level is only a typical level, not the maximum the crystal can take without damage. And that is why after selecting a crystal that fullfills the MCU requirements, it must be checked if the MCU fulfills the crystal requirements regarding the drive level. The on-board oscillators have weaker output than standard logic gates, so the external resistance is usually not necessary to limit drive level.

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Eric Vittoz was the analog IC designer who brought nanoWatt crystal oscillator methods to the Swiss watch industry.

As part of that research effort, he published a paper on "too high a gain in the amplifier will prevent crystal/circuit oscillation", where the math shows root-locus plots at high transconductances crossing the ZERO phaseshift axis, quelling the buildup of circuit resonant energy.

And here is the point of this answer: high transconductance in a small-signal model can be described as LOW RESISTANCE. And low resistances driving capacitors (e.g your 10 pF) produce small phase-shifts.

Without exactly 360 degrees phaseshift (or 0 , or 720), and net loop power-gain, the initial tenuous crystal fluctuation will not build up, because of the high Q.

Thus there must be a contiguous region of frequency with net loop power-gain.

The loop is constantly adjusting the frequency, as the PI caps change with temperature, and as that current-limiting resistor (or the transconductance) also changes with temperature.

Why? because the external phase-shift is also changing.

Popular circuits accept a wide range of external resistance (and thus are popular) because of that contiguous frequency region with net loop power-gain.

As the designer, its your task to size the amplifier Pout and Zout, and the external capacitors, and the external discrete series resistor (if any) to achieve dependable oscillation under all conditions.

Note "Zout" of the amplifier is part of your design task. That Zout must successfully interact with the PI cap.

Chances are the "size" (W/L) of the amplifier transistors vary widely from designer to designer, also dependent on the VDD range.

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