let's consider a fractional frequency divider, which is defined (wikipedia) in the following way:
A fractional-n frequency synthesizer can be constructed using two integer dividers, a divide-by-n and a divide-by-(n + 1) frequency divider. With a modulus controller, n is toggled between the two values so that the VCO alternates between one locked frequency and the other. The VCO stabilizes at a frequency that is the time average of the two locked frequencies. By varying the percentage of time the frequency divider spends at the two divider values, the frequency of the locked VCO can be selected with very fine granularity.
So, if I have a signal of frequency f0, and for instance I want to get a signal of frequency f0/(2.5), I may use it and divide half of the time by 2 and the other half by 3.
But I do not understand how can I get a signal with frequency f0/2.5 in that way. I think I get: a signal of f0/2, then a signal of f0/3, then a signal of f0/2 etc. Ok, the average frequency is f0/2.5, but the instant frequency not (and I'd say that it is the instant frequency which is important in most of the circuits).
The text speaks about VCO so I think it means that this kind of divider should be inserted in a PLL. But also in this situation I do not understand how can I get an instant frequency equal to f0/2.5.