# Fractional Frequency Divider

let's consider a fractional frequency divider, which is defined (wikipedia) in the following way:

A fractional-n frequency synthesizer can be constructed using two integer dividers, a divide-by-n and a divide-by-(n + 1) frequency divider. With a modulus controller, n is toggled between the two values so that the VCO alternates between one locked frequency and the other. The VCO stabilizes at a frequency that is the time average of the two locked frequencies. By varying the percentage of time the frequency divider spends at the two divider values, the frequency of the locked VCO can be selected with very fine granularity.

So, if I have a signal of frequency f0, and for instance I want to get a signal of frequency f0/(2.5), I may use it and divide half of the time by 2 and the other half by 3.

But I do not understand how can I get a signal with frequency f0/2.5 in that way. I think I get: a signal of f0/2, then a signal of f0/3, then a signal of f0/2 etc. Ok, the average frequency is f0/2.5, but the instant frequency not (and I'd say that it is the instant frequency which is important in most of the circuits).

The text speaks about VCO so I think it means that this kind of divider should be inserted in a PLL. But also in this situation I do not understand how can I get an instant frequency equal to f0/2.5.

A fractional frequency divider is rarely used by itself to provide a divided-down output. Although the divider you describe would on average produce an f0/2.5 signal, such a signal is rarely useful due to the large amount of jitter it has on it, as edges on the output signal obviously have to align with input signal edges.

Instead, a fractional divider is usually used within the feedback loop of a PLL.

Now this is where my treatment departs from the orthodoxy, because I think it makes it easier to understand, once you've done the required flip in thinking.

Consider a PLL, with a fixed reference frequency, a VCO, a divide by N counter, and a phase detector. Assume that it's properly designed, is stable, and has settled down. The VCO is now producing N edges for each reference edge. The N edges are getting divided down in the /N counter down to one edge, which is getting compared with the one edge from the reference input. By the the magic of feedback, and assuming stability, the right things now happen through the PSD and loop filter to control the VCO.

So now you can regard this PLL as a machine for producing N cycles of phase change at the output, for each cycle of phase change it gets through the reference port.

Now let this /N counter divide by 2 on one reference cycle, and by 3 on the other reference cycle. On average, the output is producing 2.5 cycles of phase for each reference cycle, in other words, the average output frequency is 2.5Fref.

Now consider the PLL's frequency response to modulation. Once you are above the loop bandwidth by several factors of 10, and with a steep enough loop filter, the response to the modulation can be made as small as required. Switch the divider fast enough, and the PLL will filter out the frequency mdoulation to as low a level as you specify.

Exactly the same treatment works for noise-shaping fractional-N. If you have a sequence of numbers with (a) a long term average equal to the fraction you want to multiply the reference by and (b) with negligible modulation content at low frequencies, then your PLL can filter out the modulation, and generate the long term average frequency. There are many different algorithms for producing such a sequence of numbers.

• Perfect, thank you very much! Feb 9 '20 at 16:23