# Help with understanding the mechanism of this parallel to serial shift register

Can the following shift register operation be explained step by step manner?:

How does the MUX function? What happens at each clock is a bit confusing for me to interpret. I tried to figure out my self but something is confusing especially with respect to MUX and Q.

• Have you looked up how a multiplexer normally works? The only trick here is they aren't showing the control signal that selects which input of the multiplexers is passed through to the output. Feb 11, 2020 at 3:30
• How many multiplexers are there? Is it only one? Feb 11, 2020 at 3:52

Good question!
The diagram is diagrammatic - ie it lacks some detail - one detail is crucial.
The "secret" is that they have left out one vital step.

The missing link: Prior to shifting starting a "LOAD" pulse transfers all the BIT(X) inputs to the mux outputs. When "CLOCK" is active for the first time it transfers all the bit data into the SR (shift register) as an initial parallel load.

Now "normality" takes over.
After the initial load, the muxes connect Qn data to Dn+1.
So, once the data is loaded as above each relevant clock edge transfers the output on Qn to Dn+1 so the data shifts right one stage and the far right Q becomes the output data.

• Thanks for the answer I'm trying to understand it. But could you tell me what kind of multiplexer is that? Are "MUX"s on the diagram outputs of a single multiplexer? Or is there one multiplexer between each flip flop? Feb 11, 2020 at 9:38
• @panicattack The mux is diagrammatic - it's whatever does the job. It could be a series of individual gates, or a 4 + 4 bit input to 4 bit output mux or whatever suits the designer. As an EXAMPLE ONLY the CD4053 multiplexer [datasheet here](www.ti.com/lit/ds/symlink/cd4051b.pdf) into small-necked squeeze bottles without heating it up?) has 3 x (2 to 1 ) multiplexers. You need 4 x (2 to 1) in the above cct so 2 packages of CD4053 provide 6 x (2 to 1) multiplexers. ... Feb 11, 2020 at 10:15
• ... In the 4053 diagram) page 1, bottom right) the 3 outputs can be connected either to the x or y inputs. | In this case x inputs are eg load data and y inputs are eg the previous stages Q output. The outputs go to the next D stage. Feb 11, 2020 at 10:16
• Each 2:1 mux shown above sets its output to one of its two mux inputs. Which one it sets it to is based on a control signal which is not shown in your diagram. When the invisible control signal is in one state, the register will shift to the right, taking Bit0 as its new leftmost bit. When in the other state, the register will load Bit0-Bit3 in parallel instead of shifting. Feb 11, 2020 at 13:30
• @CristobolPolychronopolis Yes. That's what I said (but differently put) in "The missing link ..." - BUT having it put again differently cannot hurt. Feb 11, 2020 at 21:50