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Power Circuit

I'm trying to design the power circuit for my project. I wanted to implement both USB and a LiPo battery to power it. I came across this circuit online but I'm struggling to understand how it works.

The VBUS is the 5V USB input, and the VBAT the LiPo. What I don't understand is the chosen MOSFET is a P-Channel Enhancement MOSFET which from my understanding means when there is a voltage applied to the gate, only then will it conduct.

However wouldn't you want a P-Channel Depletion MOSFET, as when there is no USB plugged in then you want to conduct to power the circuit? Otherwise wont you just have two power supplies operating at the same time?

Also what is the functionality of the Schottky Barrier Diode in this as well?

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  • \$\begingroup\$ Have you tried looking for a P-Channel Depletion MOSFET? Any P-Channel Depletion MOSFET, suitable or not. Tell me when you find one. Or maybe you mean JFET? Well, those have several Ohms conducting resistance. Too high. They are also difficult to find, let alone find a suitable one. \$\endgroup\$
    – DKNguyen
    Feb 11, 2020 at 3:35
  • \$\begingroup\$ Okay, so why not implement an N-Channel Depletion MOSFET? Inferring that P-Channel Depletion MOSFETS aren't available is not a valid explanation into the choice of an Enhancement MOSFET. \$\endgroup\$
    – Explorex
    Feb 11, 2020 at 3:39
  • \$\begingroup\$ Of course it is completely valid. That schematic is meant to be built and you can't build something out of part that can't be obtained. N-channels have the source terminal not connected to a fixed rail. It means lots of additional charge pump circuitry. See "high see NMOS gate drive" \$\endgroup\$
    – DKNguyen
    Feb 11, 2020 at 3:40
  • \$\begingroup\$ Obviously, but your reasoning to the choice of the component should not be 'you pick the opposite type because you can't get the first type'. They are opposites, if the opposite can be used then please explain why. \$\endgroup\$
    – Explorex
    Feb 11, 2020 at 3:44
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    \$\begingroup\$ @Explorex Regardless of what would be ideal to use, the somewhat sad reality is that depletion mode MOSFETs of either polarity are essentially not available in the current real world. There may be a few very niche exceptions but they are so very very rare that one "just doesn't" implement real world designs with them, unless there are overwhelmingly special reasons to do so. There is ALWAYS another way to do it, albeit sometimes not as elegant. The last time that I recall building something with depletion mode FETs was in 1974. Really ! :-). (46 years ago. Wow!). So -> What The Photon said ... \$\endgroup\$
    – Russell McMahon
    Feb 11, 2020 at 10:57

1 Answer 1

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If you use a depletion mode PMOS, you must apply a voltage on the gate higher than what's on the source (or drain) in order to stop it from conducting. Since the source (or drain) is often connected to the highest potential in the circuit, that would be inconvenient. In this case, the drain is connected to VBAT, so you'd need a control voltage at least slightly above VBAT (depending on the \$V_{th}\$ of the FET) to shut it off.

Using an enhancement mode PMOS, connecting the gate to the source shuts off the channel. Connecting the gate to a voltage below the source (for example, to ground, in this circuit) enables conduction through the channel. Neither of these things is particularly inconvenient to do, so we most often use enhancement mode PMOS FETS for this kind of switching application.

when there is a voltage applied to the gate, only then will it conduct.

0 V is also a voltage that can be applied to a node in a circuit. In this case, since 0 V is well below the source or drain voltage of the FET, it's a good choice for enabling the FET to conduct.

when there is no USB plugged in then you want to conduct to power the circuit?

This circuit accomplishes that by pulling the gate to ground when VUSB is not present.

Also what is the functionality of the Schottky Barrier Diode in this as well?

The diode allows current to flow from VBUS to the circuit when VBUS is present, but keeps current from VBAT from flowing back to the PMOS gate and/or other circuits connected to VBUS when VBUS is not present.

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  • \$\begingroup\$ Thankyou, this was the kind of explanation I was looking for, I appreciate it a lot. \$\endgroup\$
    – Explorex
    Feb 11, 2020 at 3:50
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    \$\begingroup\$ @Explorex, notice that the circuit is a bit tricky because they've connected the FET drain to the supply voltage rather than the source, which isn't the "normal" arrangement. Presumably we expect VBAT to be less than VBUS in cases where both are present. \$\endgroup\$
    – The Photon
    Feb 11, 2020 at 3:52

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