0
\$\begingroup\$

After my previous question, I attempted to simulate an 8-bit "parallel in serial out" shift register in LTspice as follows:

enter image description here

The above schematic is not very readable due to its size so below is the left half to see better:

enter image description here (left click to enlarge)

And here below is the right half:

enter image description here (left click to enlarge)

The B0, B1, B2, B3, B4, B5, B6, B7 are the bits of a parallel 8-bit data waiting to be sent as serial. So in the above example you can see the data is set to: 1 1 0 0 1 0 1 1. Below red plot shows this as serial output along with the clock and the shift/load' control:

enter image description here

The reason I wanted to simulate this was to understand how UART works in principle.

My questions are:

  1. Since it takes two clocks to output a bit according to the above simulation, can we say that the clock is always twice the baud-rate of the serial communication?
  2. In the simulation above, right after the eight bit data is output/sent, the rest of the bits will be zero(red plot). The data bits are always the same B0 upto B7. How can we send this data continuously like 1 1 0 0 1 0 1 1 and then again 1 1 0 0 1 0 1 1 periodically? How does it happen in real? Do we need to reset the D flip flops? after each byte?

Here is the asc file:

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\$\endgroup\$
3
  • \$\begingroup\$ A bit unrelated to your question, the schematic you posted is useless for anyone that doesn't have the custom library (74HCT.lib) and symbol(s). It looks like you made use of LTspice's sym & lib custom paths, which is convenient only for that user in particular. If you'd want to send this schematic to someone and expect that someone to be able to use it, you'd have to pack the schematic, symbol(s), and library/ies (usually an archive, for compactness). Now it may not be needed since it looks like you have an answer (which you should mark as accepted, if true, for future searches). \$\endgroup\$ Feb 12 '20 at 15:09
  • \$\begingroup\$ You say you want to simulate how a UART really works BUT are trying to do things which most UARTS do not do. | A UART will usually accept parallel data with a load signal, output that data in bit serial, usually with an added start bit and 1, 1.5 or 2 stop bits, then stop sending until another load occurs. Usually the UART is "buffered" with a short FIFO (usually one register two data words long including currently sending data) to ensure that data is always available under continuous use. There is no "magic". All the decisions about load, add start bits, shift, add stop bits, stop sending . \$\endgroup\$
    – Russell McMahon
    Feb 12 '20 at 17:07
  • \$\begingroup\$ ... are logically implemented functions using whatever method of gates etc that suit the designer. There is no one guaranteed method or circuit and you are free to implement you own. State machine, ... . || Load signal: Load daata to buffer. | If not sending: transfer buffer to active register. Set Dout low, send start bit, send 8 data bits. Set Dout high. Send stop bit (or two or ...). | If buffer has data load data and repeat. Otherwise stop. \$\endgroup\$
    – Russell McMahon
    Feb 12 '20 at 17:11
0
\$\begingroup\$

1) It does not take two clocks per bit, the waveform clearly shows output bit is updated once per clock cycle, on the rising edge, so bit rate is exactly same as clock rate.

2) You need to keep count of clock cycles and periodically reload the shift registers at a rate you want to transmit the byte again.

\$\endgroup\$
3
  • \$\begingroup\$ Reagrding "periodically reload the shift registers". What is missing in my case? Should I reset the D flip flops after each 8 clocks? \$\endgroup\$
    – pnatk
    Feb 12 '20 at 11:48
  • \$\begingroup\$ Alternatively, simply feed the serial output of the shift register back to the serial input (that dangling input on the leftmost mux in your diagram). Then you only need to do a parallel load when you want to change the pattern being sent. \$\endgroup\$
    – Dave Tweed
    Feb 12 '20 at 13:33
  • \$\begingroup\$ @DaveTweed Thanks. As you suggested, I fed the serial output of the shift register back to the floating input of the leftmost MUX. Now it sends continuous/periodic 1 1 0 0 1 0 1 1 bit pattern. Seems like LTspice is not the best program to learn digital electronics(especially in my case UART communication). \$\endgroup\$
    – pnatk
    Feb 12 '20 at 21:05

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