The Flip flops inside FPGA cannot work with both edges of the clock at the same time. That means when you have a DDR signal (Dual Data rate), which changes on both rising and falling edge of clock, you cannot connect them directly to the flip flops. For that, this module is used. This module is basically a serial to parallel converter with "D" connected to the signal which is in dual data rate and you will get the "D" value at rising edge at "QA0" and falling edge value at "QA1". Note that this works in x2 mode. That it, you will get two clock period worth of data at the two outputs (that's why SCLK is ECLK/2).
PS: The exact output will again depend on the configuration.
Internal Register block diagram:
Source : TN 1180
You can refer to Technical Note TN1180 for more details on internal diagram and other configurations.
Additional info: This module is used at the input. There are similar blocks used for generating DDR signals at the output. They are called ODDR. Xilinx FPGAs have similar blocks called IDDR, ISERDES, ODDR and OSERDES. (Refer UG471)