It is true in general. Most obvious reason is that the reset net is a very large fanout net, and removing loads from the reset net will make it easier to close timing. Additionally, freeing up the reset pin on FPGA flip-flops means that the synthesis tools can connect other signals to that pin, which could mean a reduction in the number of levels of logic, which can improve timing performance. Removing reset connections also means less nets need to be routed, alleviating some amount of routing congestion enabling the router to close timing more easily.
However, resets are important. The thing to keep in mind is that not every register needs to be reset. When you have control signals such as "valid" or "enable" alongside a wide datapath, generally you only need to worry about resetting the control signals; the much larger datapath is usually fine without any reset connections.