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The benefits of removing reset from your design are: fewer timing paths, performance and the ability to infer more dedicated hardware

Is this true or false?

I think that is false because the performance has nothing to do with fact of having/not having reset.

What do you think?

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It is true in general. Most obvious reason is that the reset net is a very large fanout net, and removing loads from the reset net will make it easier to close timing. Additionally, freeing up the reset pin on FPGA flip-flops means that the synthesis tools can connect other signals to that pin, which could mean a reduction in the number of levels of logic, which can improve timing performance. Removing reset connections also means less nets need to be routed, alleviating some amount of routing congestion enabling the router to close timing more easily.

However, resets are important. The thing to keep in mind is that not every register needs to be reset. When you have control signals such as "valid" or "enable" alongside a wide datapath, generally you only need to worry about resetting the control signals; the much larger datapath is usually fine without any reset connections.

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The answer to your question depends a great deal on how the reset is actually implemented in a given FPGA's architecture.

It the reset logic is hardwired into the FPGA's logic then it would probably not make any difference whether the reset was used or not. On the other hand, if a synchronous reset is used and the reset signal is merged into the other logic then it is possible that the presence of the reset would have a negative effect on the path delay and on the required logic resources.

It's always dangerous to try to make a blanket statement about such things. It's a complex world out there.

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All the above answers are correct and i think i have some more things to add about correct usage of resets in context of FPGA/ASIC as resets architectures are complex involving reset sequencing and Reset domain crossings once cannot give direct suggestions

https://www.eetimes.com/how-do-i-reset-my-fpga/#


I think that is false because the performance has nothing to do with fact of having/not having reset.

*** please go through this 2 part article ,Atleast read 2 article for the above assumption

https://forums.xilinx.com/t5/Adaptable-Advantage-Blog/Demystifying-Resets-Synchronous-Asynchronous-other-Design/ba-p/882252

https://forums.xilinx.com/t5/Adaptable-Advantage-Blog/Demystifying-Resets-Synchronous-Asynchronous-and-other-Design/ba-p/887366

http://www.sunburst-design.com/papers/CummingsSNUG2003Boston_Resets.pdf

http://www.sunburst-design.com/papers/CummingsSNUG2002SJ_Resets.pdf

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