How are external interrupts handled by microcontrollers?

My question is general to micro-controllers, but if it is architecture specific, leans to ARM- based micro-controllers.

Assuming we have 2 interrupt pins PIN1 and PIN2 set to interrupt when the pin state change. At start both of them are in low state, PIN1 is then interrupted as the signal pulls high. In software the uC is still processing data although the data is very small due to coincidence PIN2 pulls HIGH which in most will be missed since there is still an interrupt being processed.

Now when the interrupt on PIN1 exits will PIN2 immediately trigger another interrupt since its state changed?


since the question is much broader than expected i have chosen a micro - controller for the sake of the question. The micro - controller is: AT91SAM3X8E the one used in arduino due. And will be programmed using the ARDUINO IDE. I have project that uses this chip and knowledge on its interrupt might come in handy.

I have always thought there will be a standardized way.

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    \$\begingroup\$ This is under code control i.e. how you set up the interrupts in your code. \$\endgroup\$
    – Andy aka
    Commented Feb 13, 2020 at 13:41
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    \$\begingroup\$ not only that, but pins are typically peripherals, so it's not even only specific to ARM, but even to the specific microcontroller you're using. You'll need to refer to the programming guide of the microcontroller. \$\endgroup\$ Commented Feb 13, 2020 at 13:43
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    \$\begingroup\$ In addition to the other comments, interrupts can have different priorities which can significantly change what happens from the default settings of all (IRQ type) interrupts having equal priorities. \$\endgroup\$ Commented Feb 13, 2020 at 13:46
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    \$\begingroup\$ My question seems to be broader than i thought, Andyaka interrupts are handled by a library which might be tricky for me to understand quickly and what MarcusMüller said if its chip specific it would be time consuming to understand them all. so my best bet is to test the chip themselves if it handles it the way i want to \$\endgroup\$
    – Jake quin
    Commented Feb 13, 2020 at 14:03
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    \$\begingroup\$ so as you can see this is a cortex-m3 so you need the cortex-m3 technical reference manual and that indicates armv7-m architectures so you need the armv7-m architectural reference manual before you start any software development as well as the documentation for this chip. ARM does not have GPIO as pointed out, so you have to look at how the gpio based interrupts are wired into the arm core, if on the same interrupt line then first off how does the chip logic (as in not ARM) handle that situation and then how does arm react, if you try to return from an interrupt and the same interrupt line \$\endgroup\$
    – old_timer
    Commented Feb 13, 2020 at 20:04

4 Answers 4


The behavior of these external interrupts is not part of the ARM architecture itself. This is determined by the individual chip manufacturers. The answer depends on whether the interrupts have the same or different priority, whether they are triggered by edges on the pins or levels on the pins, and what happens if a level-sensitive interrupt is serviced but the pin remains in the interrupting state.

  • \$\begingroup\$ For the M series, the NVIC is the usual approach (and defined by ARM); the issue is that how the interrupts are presented is vendor dependent. \$\endgroup\$ Commented Feb 13, 2020 at 15:17

When an active interrupt is detected, the processor will generally start processing instructions in a different location. This is usually a predetermined location or a location whose address is stored in a predetermined location.

If an interrupt is being processed and another interrupt is detected:

-- If the second interrupt is at the same or lower priority, it will be processed when the first interrupt routine is complete.

-- If the second interrupt is at a higher priority, the first interrupt routine will itself be interrupted and will continue only after the second interrupt routine is done.

Note that some of these processes, such as manipulation of the interrupt flags, may not be automatic so the interrupt routine may have to handle them explicitly. This will depend on the architecture.


In ARM cortex M3, there is a concept same, where the stack pushed data will not be retrieved back because the system already knows that it has to serve interrupt 2. It is called tail chaining.


You have to narrow down your question to your MCU atleast, else this answer has to be a book and a page more.

Why we can't tell exactly what will Happen

  1. Interrupts can have same priority
  2. Interrupts can be in same group priority but different level
  3. Interrupt 1 has higher priority than interrupt 2
  4. Interrupt 2 has higher priority than interrupt 1
  5. Second interrupt was already serving
  6. Interrupt was already pending
  7. Interrupt was disabled

And so on..
For every case above there is a defined way which depends on the architecture. ARM Vs SHARC vs many others..

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    \$\begingroup\$ "there is a concept same as the above" Please don't refer to above/below in your answer, the order your answer appears changes based on the readers sort order, votes, acceptance, etc. \$\endgroup\$
    – Ron Beyer
    Commented Feb 13, 2020 at 15:02
  • \$\begingroup\$ @RonBeyer updated \$\endgroup\$
    – User323693
    Commented Feb 13, 2020 at 15:08

Multiple external interrupts will not chain together if the IO share interrupt flags which get cleared when handling one or the other. Read a specific manufacturer datasheet to see how multiple GPIO might share interrupt lines since it os overkill to have a dedicated interrupt for each GPIO.

In general pending interrupts (not just external) should run when the current one is done, in order of priority. ARM Cortex has a feature called tail-chaining to speed this up. You can even enable things so higher priority interrupts interrupt a lower priority interrupt currently running. So-called nested interrupts but it makes programming very tricky.

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    \$\begingroup\$ As far as I know the preemption (nesting of interrupts) is standard on ARM Cortex-M devices (if you have different priorities). \$\endgroup\$
    – Arsenal
    Commented Feb 13, 2020 at 15:29
  • \$\begingroup\$ @Arsenal I'll have to check because I don't think I saw pre-emption weirdness in my code despite assigning priorities. \$\endgroup\$
    – DKNguyen
    Commented Feb 13, 2020 at 15:30

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